DOMINO LOGIC CIRCUIT (VLSI)

Problems of dynamic logic circuits and how it is solved by Domino logic circuits, is explained over here. Why it is called domino and how domino logic works, that also explained here.

1. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
1
Digital Integrated
Circuits
A Design Perspective
Designing Combinational
Logic Circuits
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
November 2002.

2. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
2
Issues in Dynamic Design 1:
Charge Leakage
C
L
Clk
Clk
Out
A
M
p
M
e
Leakage sources
CLK
V
Out
Precharge
Evaluate
Dominant component is subthreshold current

3. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
3
Solution to Charge Leakage
C
L
Clk
Clk
M
e
M
p
A
B
Out
M
kp
Same approach as level restorer for pass-transistor logic
Keeper

4. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
4
Issues in Dynamic Design 2:
Charge Sharing
C
L
Clk
Clk
C
A
C
B
B=0
A
Out
M
p
M
e
Charge stored originally on
C
Lis redistributed (shared)
over C
Land C
Aleading to
reduced robustness

5. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
5
Charge Sharing
C
L
Clk
Clk
C
A
B=0
A
V
Out
V
X
Slide by Kia

6. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
6
Charge Sharing
C
L
Clk
Clk
C
A
B=0
A
V
Out
V
X
Slide by Kia

7. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
7
Charge SharingM
p
M
e
V
DD

Out

A
B = 0
C
L
C
a
C
b
M
a
M
b
X
C
L
V
DD
C
L
V
out
tC
a
V
DD
V
Tn
V
X
–+=
or
V
out
V
out
tV
DD
–
C
a
C
L
-------- V
DD
V
Tn
V
X
––==
V
out
V
DD
C
a
C
a
C
L
+
----------------------



–=
case 1) if V
out < V
Tn
case 2) if V
out > V
Tn
B=0
Clk
X
C
L
C
a
C
b
A
Out
M
p
M
a
V
DD
M
b
Clk M
e

8. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
8
Solution to Charge Redistribution
Clk
Clk
M
e
M
p
A
B
Out
M
kp
Clk
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)

9. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
9
Issues in Dynamic Design 3:
Backgate Coupling
C
L1
Clk
Clk
B=0
A=0
Out1
M
p
M
e
Out2
C
L2
In
Dynamic NAND Static NAND
=1
=0

10. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
10
Backgate Coupling Effect-1
0
1
2
3
0 2 4 6
Time, ns
Clk
In
Out1
Out2

11. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
11
Issues in Dynamic Design 4: Clock
Feedthrough
C
L
Clk
Clk
B
A
Out
M
p
M
e
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above V
DD. The fast rising
(and falling edges) of the
clock coupleto Out.

12. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
12
Clock Feedthrough-0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In
1
In
2
In
3
In
4
Out
In &
Clk
Out
Time, ns
Clock feedthrough
Clock feedthrough

13. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
13
Other Effects
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)

14. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
14
Cascading Dynamic Gates
Clk
Clk
Out1
In
M
p
M
e
M
p
M
e
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2
V
V
Tn
Only 0 1 transitions allowed at inputs!

15. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
15
Domino Logic
In
1
In
2 PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4 PDN
In
5
M
e
M
p
Clk
Clk
Out2
M
kp
1 1
1 0
0 0
0 1

16. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
16
Properties of Domino Logic
Only non-inverting logic can be implemented
Very high speed
static inverter can be skewed, only L-H transition
Input capacitance reduced –smaller logical effort
Better noise margin

17. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
17
Why Call it Domino?
Clk
Clk
In
iPDN
In
j
In
i
In
j
PDN In
iPDN
In
j
In
iPDN
In
j
Like falling dominos!

18. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
18
Footer needed?
Clk
Clk
Out1
In
Clk
Clk
Out2
Slide by Kia (fig by Rabaey)

19. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
19
Designing with Domino Logic
M
p
M
e
V
DD
PDN
Clk
In
1
In
2
In3
Out1
Clk
Mp
M
e
VDD
PDN
Clk
In
4
Clk
Out2
M
r
VDD
Inputs = 0
during precharge
Can be eliminated!

20. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
20
Footless Domino
The first gate in the chain needs a foot switch
Precharge is rippling –short-circuit current
A solution is to delay the clock for each stageV
DD
Clk M
p
Out
1
In
1
1 0
V
DD
Clk M
p
Out
2
In
2
V
DD
Clk M
p
Out
n
In
nIn
3
1 0
0 1 0 1 0 1
1 0 1 0

21. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
21
Domino Layout
Slide by Kia

22. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
22
np-CMOS
In
1
In
2 PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4 PUN
In
5
M
e
M
pClk
Clk
Out2
(to PDN)
1 1
1 0
0 0
0 1
Only 0 1 transitions allowed at inputs of PDN
Only 1 0 transitions allowed at inputs of PUN

23. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
23
NORA Logic
In
1
In
2 PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4 PUN
In
5
M
e
M
pClk
Clk
Out2
(to PDN)
1 1
1 0
0 0
0 1
to other
PDN’s
to other
PUN’s
WARNING: Very sensitive to noise!

24. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
24
Differential (Dual Rail) Domino
A
B
M
e
M
p
Clk
Clk
Out = AB
!A !B
M
kp
Clk
Out = AB
M
kpM
p
Solves the problem of non-inverting logic
1 0 1 0
on
off

25. EE141© Digital Integrated Circuits
2nd
Combinational Circuits
25
Multiple-Output Domino