DRAM update ppt 1 & 2 .pptx

DRAM project

1. Project - DRAM Garima Choudhary Sambhav Sharma

2. Write Operation Hold Operation Read Operation WL = 1 (Access transistors turned ON) Apply voltage to Bit Line. (Logic 1 = V and Logic 0=GND) Accordingly, capacitor will be charged to (V - Vth) or discharged to GND. WL= 0 Access transistors turned OFF. Charge is held on a capacitor. Leakage currents due to discharging of a capacitor. I = Q/T = CV/T Determine T to find out the hold time: T = CV/I Accordingly, determine the refresh rate (1/2T_hold) WL = 1 Access transistors turned ON. Charge of the capacitor would get distributed with bit line capacitance. This will change the bit line voltage as 1 or 0

3. 1T1C Read and Write operation Schematic And Simulation

4. Write operation

5. Hold operation

6. Transmission Gate Circuit to avoid the Vth Drop

7. Quintuple-row activation: activating five rows at the same time to wish to accomplish a vector majority

8. Charge Sharing

9. RowClone: fast parallel mode of copying data from source row to destination row within the same subarray

10. Calculating the majority function of A , B , and C in to obtain C out while using the dual-contact cell to store C out bar in the same operation. C out = Majority ( A , B , C in ) S = Majority ( A , B , C in , C out bar , C out bar )