dsd for traditional system design for elecronics.ppt

Traditional system design

1. TRADITIONAL SYSTEM
DESIGN
•AVAILABILTY OF THE OFF THE SHELF
COMPONENTS DETERMIN THE
IMPLEMENTATION
•DESIGN PARTIONING ACROSS BOARDS IS
A CRUCIAL DESIGN PHASE
•PACKAGE DESIGN IS DESIDED LATER
•SOFTWARE DESIGN & DEVELOPMENT
STARTED LATER
•DESIGN CYCLES WERE 3 OR MORE
YEARS

2. CONTINUED……
•COMPONENTS BECOMING
OBSOLETEWAS A LURKING DANGER
•CHANGES IN SPECIFICATIONS
INVOLVED COSTLY DESIGN
ITERATIONS

3. FPGAs & GATE ARRAYS
•HIGHLY FEXIBLE
•LOW ENERGY COST
•SHORTER DEVELOPMENT CYCLE
•LOW RISK
•NEGLIGIBLE ITERATION COST
•EMINENTLY SUITABLE FOR LOW
VOLUMES
•NO COMLICATED & ELABORATE TEST
DESIGN

4. Programmable logic device
(PLD)?
It is an IC used to build digital circuits.
Unlike a logic gate which has a fixed function, a
PLD has an undefined function at the time of
manufacture. Before the PLD can be used in a
circuit it can be configured by the user to perform
a logic function by programming it.

5. TYPES
PROM
FIXED AND ARRAY &
PROGRAMMABLE OR ARRAY
PLA
AND & OR ARRAY PROGRAMMABLE
PAL
PROGAMMABLE AND &FIXED OR

6. Early programmable logic
In 1970, TEXAS INSTRUMENTS developed a
mask-programmable IC, the TMS2000,
was programmed by altering the metal
layer during the production of the IC.
TI coined the term
PROGRAMMABLE LOGIC ARRAY
for this device.

7. ROM as a PLD
Before PLDs were invented, (ROM) chips were
used to create arbitrary COMBINATIONAL
LOGIC functions

10. Programmable Array Logic

11. PAL devices consists of a small PROM
(programmable read-only memory)
core and additional output logic used to
implement particular desired logic
functions with few components

15. Programming languages
•PALASM
•ABEL
•VHDL

16. PALASM

17. INTRODUCTION
•PALASM IS A SOFTWARE WHICH
CONVERTSAN INPUT PLD DESIGN
INTO A JEDEC FILE

18. JEDEC
JOINED ELECTRON DEVICE
ENGINEERING COUNCIL

19. A JEDEC FILE
•SPECIFIES WHICH FUCES ARE TO BE
BLOWN ON THE TARGET DEVICE
•CAN BE USED TO PROGRAM PLDS ON
A PROGRAMER

20. ROLE OF PALASM
•HIGH LEVEL LANGUAGE
•COMPILER
•MACHINE CODE
•PALASM SOURCE
•PALASM
•JEDEC FILE

22. OPERATIONSSEQUENCE
STEP1
INPUT SOURCE FILE
•CHECK INPUT
SYNTAX
•EXPAND FUNCTIONS
•MINIMIZE EQUATIONS
•ASSEMBLE
•SIMULATE
•TRACEFILE OUTPUT
OR WAVEFORMS
STEP2
INPUT SOURCE FILE
•CHECK INPUT
SYNTAX
•EXPAND FUNCTIONS
•MINIMIZE EQUATIONS
•ASSEMBLE
•JEDEC FILE AND FUSE
MAP

23. CPLD

24. Field-programmable gate array
•A field programmable gate array
(FPGA) is a semiconductor device
containing programmable logic
components and programmable
interconnects.

25. •The programmable logic components
can be programmed to duplicate the
functionality of basic logic gates such as
AND, OR, XOR,NOT or more complex
combinational functions such as decoders
or simple math functions.

26. In most FPGAs, these
programmable logic components
(or logic blocks, in FPGA ) also
include memory elements, which
may be simple
flipflops or more complete
blocks of memories.

27. Architecture
The basic architecture consists of
an array of configurable logic blocks (CLBs)
and routing channels. Multiple I/Opads may fit
into the height of One row or the width of one
column. Generally, all the routing channels have
the same width (number of wires).
An application circuit must be mapped into an
FPGA with adequate resources.

31. THANK YOU