efficient hardware accelerator design for crypto

efficient hardware accelerator design for crypto

1. Done By Shahad M. Hussein AL- Zubaidi Supervised By Atefah Salemi December/ 2022 Efficient Hardware Accelerator Design For Skein Cryptograghy Algorithm 1

2. Contents Abstract Introduction Chained cryptographic hash function Skein algorithm Zynq devices Simulation result The specification of the proposed SKEIN algorithm Conclusion References 2

3. Abstract Nowadays, there has been an increasing demand in cryptocurrency popularity. As an example of an ASIC-resistant hashing algorithm Lyra2REv2 and basically Skein algorithm as one of the main hashing blocks of that is considered in this paper. FPGAs are low risk, cost efficient hardware for implementing the ASIC resistance hashing algorithms. 3

4. Introduction Modern decentralized information systems and networks built on the blockchain technology are increasingly distributes and uses in various applications. Blockchain technologies are used in the construction of cryptocurrencies, for the construction of decentralized systems of different purpose and functional tasks. 4

5. Chained cryptographic hash function * ASIC resistance is achieved by using hashing algorithms that are highly serial, memory-intensive, and parameterizable so that a manufactured ASIC can easily be made obsolete by changing some of the parameters. * Since the cost of manufacturing new ASICs whenever some parameters change is prohibitive, GPU mining of ASIC-resistant cryptocurrencies is generally * much more low-risk and cost-effective. * A prime example of an ASIC-resistant hashing algorithm is Lyra2REv2 * FPGAbased miners, on the other hand, are flexible, energy efficient, * and readily available to the general public at reasonable prices. 5

6. Skein algorithm * Skein is a family of hash functions which could have three diverse 256, 512, and 1024 bits internal state size. * Skein-512 is the main goal of this thesis and its hardware implementation is considered in this work. * Skein-256 is an out-of-memory version comparing with the others. It can be implemented with about 100 bytes of RAM. * The Skein-1024 which is an ultra-conservative version among the others has internal state size which is twice that of Skein-512, making it less prone to bugs. * Even if skein-512 is cracked in a future attack, skein-1024 will likely remain secure. * Comparing the speed, Skein-1024 can also run almost twice as fast as Skein-512 on special hardware implementations. 6

7. Zynq devices * Contains both FPGA and ARM and are SOC devices. * Both ARM and FPGA parts could be used for co-communication. * AXI-buses are used for signal transmission between FPGA/ARM of the Zynq . 7

8. Simulation result * The idata is the data provided to the skein via input file * The odata will be written in the file and has the value shown in the figure 8

9. The specification of the proposed SKEIN algorithm * The maximum achievable clock frequency for the implementation is 140 MHz. * As mentioned earlier the number of cycles for the 8 unrolled pipeline structure is 10. * The power consumption of the design is 0533 watt with hash rate of 14MHash/s. 9

10. Conclusion * In this paper a SOC implementation of the Skein algorithm is presented. * To improve the parameters of the hardware design a software/hardware partitioning design is offered. * Random data set, padding of the input message and subkey generation of the algorithm performed in the PS side, * The other blocks including control finite state machine, parallel 8 round unrolled structure are implemented in the hardware of the SOC. * For hashing multiple unique messages simultaneously, the pipelined architecture greatly increases the throughput. The clock frequency and hash rate of the design is 140 MHz and 14 respectively. 10

11. References [1] S. Nakamoto , "Bitcoin: A peer-to-peer electronic cash system," Decentralized Business Review, p. 21260, 2008. [2] T. Peyrin , "Security analysis of extended sponge functions," in Talk at the workshop Hash functions in cryptology: theory and practice, 2008. [3] J.-P. Aumasson , W. Meier, and R. C.-W. Phan, "The hash function family LAKE," in International Workshop on Fast Software Encryption, 2008, pp. 36-53: Springer. [4] A. Regenscheid et al., Status report on the first round of the SHA-3 cryptographic hash algorithm competition. Citeseer , 2009. [5] N. Ferguson et al., "The Skein hash function family. Submission to NIST (Round 3)(2010)," URL http://www. skein-hash. info/sites/default/files/skein1, vol. 3. [6] A. Schorr , "Performance analysis of a scalable hardware fpga skein implementation," 2010. 11

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