electronics and elctrical documents with logic circuit

electronics and elctrical documents with logic circuit

1. Logic Circuits
Course Code: EEEG 214
Ch-5
4/8/22 Asst Prof Kamal Chapagain, KU

2. Introductions- IC digital logic families
•RTL（Resistor-transistor logic）
•DTL（Diode-transistor logic）
•TTL（Transistor -transistor logic）
•ECL（Emitter-coupled logic）
•MOS（Metal-oxide semiconductor）
•CMOS（Complementary Metal-oxide semiconductor）
4/8/22
Positive logic: H is set to be binary 1
Negative logic: L is set to be binary 1
Asst Prof Kamal Chapagain, KU

3. Parameters of Logic families
•fan-out
•The no. of standard loads can be connected to
the output of the gate without degrading its
normal operation
•Sometimes the term loading is used
•Power dissipation
•The power needed by the gate
•Expressed in mW
•Propagation delay
•The average transition-delay time for the signal
to propagate from input to output when the
binary signal changes in value
•Noise margin
•The unwanted signals are referred to as noise
•Noise margin is the maximum noise added to an
input signal of a digital circuit that does not
cause an undesirable change in the circuit output

4/8/22 Asst Prof Kamal Chapagain, KU

4. Fan-out Calculation
(High output: example)
4/8/22
Fan-out Calculation
(Low output: example)
Asst Prof Kamal Chapagain, KU

5. Power dissipation
4/8/22 Asst Prof Kamal Chapagain, KU
Propagation delay
50%
V
H

50%
V
H

50%
V
H

50%
V
H

For standard TTL

6. Noise margin
4/8/22 Asst Prof Kamal Chapagain, KU

7. RTL (Resistor Transistor Logic)
•RTL is the first logic family which
is not available in monolithic form.
•The basic circuit of the RTL logic
family is the NOR.
•Each input is associated with one
resistor and one transistor.
•The collector of the transistor are
tied together at the output.
•The voltage levels for the circuit are
0.2v for the low level and from 1 to
3.6v forthe high level.

4/8/22 Asst Prof Kamal Chapagain, KU
A B
Y=
̅
�
̅̅̅
+
̅̅̅
�
̅
00 1
0 1 0
1 0 0
1 1 0

8. RTL fan-out derivation
4/8/22 Asst Prof Kamal Chapagain, KU

9. 4/8/22
RTL fan-out derivation
Asst Prof Kamal Chapagain, KU

10. 4/8/22
RTL fan-out derivation
Asst Prof Kamal Chapagain, KU

11. RTL fan-out derivation
4/8/22 Asst Prof Kamal Chapagain, KU

12. RTL Fan-out calculation (Example)
4/8/22 Asst Prof Kamal Chapagain, KU

13. RTL Power-Dissipation
4/8/22 Asst Prof Kamal Chapagain, KU

14. Propagation Delay
•Propagation delay describes the
amount of time between a change
at the 50% point input to cause a
change at the 50% point of the
output.

•The high-to-low propagation
delay, τPHL, and the low-to-high
propagation delay, τPLH, are
usually not equal
4/8/22 Asst Prof Kamal Chapagain, KU

15. DTL Logic
•The DTL circuit shown in the figure in side, consists of three stages: an
input diode logic stage (D1, D2 and R1), an intermediate level shifting stage
(R3 and R4), and an output common-emitter amplifier stage (Q1 and R2).
•If both inputs A and B are high (logic 1), then the diodes D1 and D2 are
reverse biased. Resistors R1 and R3 will then supply enough current to turn
on Q1 (drive Q1 into saturation) and also supply the current needed by R4.
•There will be a small positive voltage on the base of Q1 (V
BE
, about 0.3 V for
germanium and 0.6 V for silicon).
•The turned on transistor's collector current will then pull the output Q1 low
(logic 0; V
CE(sat)
, usually 0.2 volt).
•If either or both inputs are low, then at least one of the input diodes
conducts and current due to V+ flows towards either A or B.
•Drop across D1 or D2 can not turn on Q1 because the resistance R3 and R4
acts as a voltage divider that makes Q1's base voltage negative and
consequently turns off Q1. Q1's collector current will be essentially zero, so
R2 will pull the output voltage Q high (logic 1).
4/8/22

A

B

00 1
0 1 1
1 0 1
1 1 0
Asst Prof Kamal Chapagain, KU

16. Basic DTL
Comparing to previous fig,
Why –v potential and resistors
R3, R4 are removed?


Circuit analysis:

Asst Prof Kamal Chapagain, KU

17. Calculation of Noise Margins
4/8/22 Asst Prof Kamal Chapagain, KU

18. Modified DTL (implementing Transistor)
4/8/22 Asst Prof Kamal Chapagain, KU

19. Modified DTL (implementing Transistor)

20. TTL (Transistor Transistor Logic)
•The Transistor-Transistor Logic (TTL) is a logic family made up
of BJTs (bipolar junction transistors). As the name suggests,
the transistor performs two functions like logic as well as
amplifying. The best examples of TTL are logic gates namely
the 7402 NOR Gate & the 7400 NAND gate.
•TTL logic includes several transistors that have several
emitters as well as several inputs. The types of TTL or
transistor-transistor logic mainly include Standard TTL, Fast
TTL, Schottky TTL, High power TTL, Low power TTL &
Advanced Schottky TTL.
•The designing of TTL logic gates can be done with resistors
and BJTs. There are several variants of TTL which are
developed for different purposes such as the
radiation-hardened TTL packages for space applications and
Low power Schottky diodes that can provide an excellent
combination of speed and lesser power consumption.
4/8/22 Asst Prof Kamal Chapagain, KU
Standard TTL

A

B

00 1
0 1 1
1 0 1
1 1 0

21. TTL (Transistor Transistor Logic): Working
4/8/22 Asst Prof Kamal Chapagain, KU
•When any one input (A and B) LOW:
•BE junction of Q1 is forward biased. But IC for Q1 is only leakage current of D2 which is
very small, and Q1 is in saturation. So voltage at collector of Q1 is nearly 0.2V and
insufficient voltage to forward bias for Q2 and subsequently Q3 is off. i.e Output is VCC,
i.e HIGH logic level.
•With all inputs at HIGH (VCC) :
•BE junction of Q1 is reverse biased. Current flows from VCC through R1, forward biased
BC junction of Q1, Q2 and BE junction of Q3. This current is sufficient to saturate Q3
resulting LOW logic level at the output of the gate.
•Role of Q2:
•Q2 acts as phase splitter. Voltage at C & E of Q2 are 180 degree out of phase. Thus when
there is LOW at E of Q2 to turn off Q3, there is HIGH at C of Q2 to turn on Q4 and vice
versa.
•Role of D1:
•The diode D1 is required to avoid an indeterminate output level. With LOW level at
output, both Q2 and Q3 are saturated. Their collector voltages w.r.t. ground are 0.9V and
0.2V respectively. The voltage 0.9V in absence of D1 turns on Q4. Then current will be
diverted from collector of Q2 to base of Q4 and thus Q2 will come out of saturation. Then
both Q3 and Q4 will be conducting resulting in indeterminate output level

22. Fanout-TTL
•Assignment:
•With output Low: M= 54
•With output High: M=175 (for two emmiter)
4/8/22 Asst Prof Kamal Chapagain, KU

23. Fanout-TTL
•Assignment:
•With output Low: M= 54
4/8/22 Asst Prof Kamal Chapagain, KU

24. Types of Transistor-Transistor Logic
•TTLs are available in different types and their classification is done
based on the output like the following.
•Standard TTL
•Fast TTL
•Schottky TTL
•High Power TTL
•Low Power TTL
•Advanced Schottky TTL.
4/8/22 Asst Prof Kamal Chapagain, KU
https://www.electrical4u.com/transistor-transistor-logic-or-ttl/

25. Comparisons:
4/8/22 Asst Prof Kamal Chapagain, KU
S
NO.
RTL Logic DTL Logic TTL Logic
1 Built with Resistor and TransistorBuilt with Diode and
Transistor
Built with Transistors
2 Slow Response Better than RTL Logic Much better than RTL and
DTL
3 High Power Loss Low Power Loss Low Power Loss
4 Very simple in construction and
operation
Simple in construction and
operation
Complex in construction and
operation
5 RTL Logic used in old computersDTL logic used in basic
digital circuits, switching
circuits
All the modern digital
circuits, Integrated Circuits
are mostly built with TTL
Logic

26. MOS & CMOS: MOSFET aka MOS and
Complementary MOS aka CMOS
•MOSFET can be classified into Enhancement type MOSFET and Depletion type MOSFET. Each of these types
are further divided into N-channel MOSFET and P-channel MOSFET.
The main difference between Enhancement Mode MOSFET and Depletion Mode MOSFET is that in depletion mode, the
channel is already formed i.e., it acts as a Normally Closed (NC) switch and in case of enhancement mode, the channel is not
formed initially i.e., a Normally Open (NO) switch.
4/8/22 Asst Prof Kamal Chapagain, KU

27. Working of a MOSFET as a Switch
•This is a simple circuit, where an N-Channel
Enhancement mode MOSFET will turn ON or
OFF a light. In order to operate a MOSFET as a
switch, it must be operated in cut-off and
linear (or triode) region.
•Assume the device is initially OFF. The voltage
across Gate and Source i.e., V
GS
is made
appropriately positive (technically speaking,
V
GS
> V
TH
), the MOSFET enters linear region
and the switch is ON. This makes the Light to
turn ON.
•If the input Gate voltage is 0V (or technically <
V
TH
), the MOSFET enters cut-off state and
turns off. This in turn will make the light to
turn OFF.

4/8/22 Asst Prof Kamal Chapagain, KU

28. Power dissipation: An important factor
•An important factor to consider is the power dissipation of the MOSFET.
Consider a MOSFET with a Drain to Source Resistance of 0.1Ω. In the above
case i.e., a 12W LED driven by a 12V supply will lead to a drain current of 1A.
•Hence the power dissipated by the MOSFET is P = I
2
* R = 1 * 0.1 = 0.1W.
•This seems to be a low value but if you drive a motor using the same
MOSFET, the situation is slightly different. The starting current (also called
as in-rush current) of a motor will be very high.
•So, even with R
DS
of 0.1Ω, the power dissipated during the start-up of a
motor will still be significantly high, which may lead to thermal overload.
Hence, R
DS
will be a key parameter to select a MOSFET for your application.
•Also, when driving a motor, the back emf is an important factor that has to
be considered while designing the circuit.
•One of the main advantages of driving a motor with MOSFET is that an Input
PWM signal can be used to smoothly control the speed of the motor.


4/8/22 Asst Prof Kamal Chapagain, KU

29. NMOS/PMOS Logic
4/8/22 Asst Prof Kamal Chapagain, KU

30. NMOS+PMOS = CMOS Logic
Case-1 : V
A
– Low & V
B
– Low
V
A
– Low: pMOS1 – ON; nMOS1 – OFF
V
B
– Low: pMOS2 – ON; nMOS2 – OFF
Case-2 : V
A
– Low & V
B
– High
V
A
– Low: pMOS1 – ON; nMOS1 – OFF
V
B
– High: pMOS2 – OFF; nMOS2 – ON
Case-3 : V
A
– High & V
B
– Low
V
A
– High: pMOS1 – OFF; nMOS1 – ON
V
B
– Low: pMOS2 – ON; nMOS2 – OFF
Case-4 : V
A
– High & V
B
– High
V
A
– High: pMOS1 – OFF; nMOS1 – ON
V
B
– High: pMOS2 – OFF; nMOS2 – ON
Similarly for CMOS NOR
CMOS NAND
CMOS NOR
Case-1 : V
A
– Low & V
B
– Low
V
A
– Low: pMOS1 – ON; nMOS1 – OFF
V
B
– Low: pMOS2 – ON; nMOS2 – OFF
http://www.vlsifacts.com/nand-gate-using-cmos-technology/
4/8/22 Asst Prof Kamal Chapagain, KU