Gate level design, switch logic, pass transistors

Gate level design

1. 6 / 3 / 2 15 274 UNIT-I II GATE LEVEL DESIGN Topics Logic gates and other complex gates Switch logic Alternate gate circuits Time delays Driving large capacitive loads Wiring capacitances Fan-in and fan-out, Choice of layers

2. NMOS Gate construction A B NMOS devices in series implement a NAND function A • B A B 6 / 3 / 2 15 NMOS devices in parallel implement a NOR function A + B A B F 1 1 1 1 1 1 1 A B F 1 1 1 1 1 275

3. PMOS Gate construction A B PMOS devices in parallel implement a NAND function B A A + B A • B PMOS devices in series implement a NOR function A B F 1 1 1 1 1 1 1 6 / 3 / 2 15 A B F 1 1 1 1 1 276

4. Parasitics and Performance Consider the following layout: What is the impact on performance of pa r asi t i cs At point a (VDD rail)? At point b (input)? At Point c (output)? b a c 6 / 3 / 2 15 277

5. Parasitics and Performance a - power supply connections capacitance - no effect on delay resistance - increa b ses delay (see p. 135) minimize by reducing difffusion length minimize using parallel vias a c 6 / 3 / 2 15 278

6. Driving Large Loads Off-chip loads, long wires, etc. have high capacitance Increasing transistor size increases driving ability (and speed), but in turn increases gate capacitance Solution: stages of progressively larger transistors Use nopt = ln(Cbig/Cg). Scale by a factor of a=e 6 / 3 / 2 15 281

7. 6 / 3 / 2 15 282 Summary: Static CMOS Advantages High Noise Margins (VOH=VDD, VOL=Gnd) No static power consumption (except for leakage) Comparable rise and fall times (with proper sizing) Robust and easy to use Disadvantages Large transistor counts (2N transistors for N inputs) Larger area More parasitic loading (2 transistor gates on each input) Pullup issues Lower driving capability of P transistors Series connections especially problematic Sizing helps, but increases loading on gate inputs

8. 6 / 3 / 2 15 283 Alternatives to Static CMOS Switch Logic nmos Pseudo-nmos Dynamic Logic Low-Power Gates

9. Switch Logic Key idea: use transistors as switches Concern: switches are bidirectional A ND A B OR 6 / 3 / 2 15 284

10. Switch Logic - Pass Transistors Use n-transistor as “switches” “Threshold problem” Transistor switches off when Vgs < Vt VDD input -> VDD-Vt output “pecial gate needed to “restore” values IN: V DD 6 / 3 / 2 15 285 A: V DD OUT: V D D - V tn

11. Switch Logic - Transmission Gates A A 6 / 3 / 2 15 286 Complementary transistors - n and p No threshold problem Cost: extra transistor, extra control input Not a perfect conductor! A’ A’

12. Switch Logic Example - 2-1 MUX IN 6 / 3 / 2 15 287

13. Charge Sharing Consider transmission gates in series Each node has parasitic capacitances Problems occur when inputs change to redistribute charge Solution: design network so there is always a path from VDD or Gnd to output 6 / 3 / 2 15 288

14. Aside: Transmission Gates in Analog Transmission Gates work with analog values, too! Example: Voltage-Scaling D/A Converter 6 / 3 / 2 15 289

15. NMOS Logic Used before CMOS was widely available Uses only n transistors Normal n transistors in pull- down network depletion-mode n transistor (Vt < 0) used for pull-up "ratioed logic" required Tradeoffs: Simpler processing Smaller gates higher power! Additional design considerations for ratioed logic Passive Pullup Device: depletion Mode n-transistor (V t < 0) OUT 6 / 3 / 2 15 290 Pulldo w n Network

16. Pseudo-nmos Logic Same idea, as nmos, but use p- transistor for pullup "ratioed logic" required for proper design (more about this next) Tradeoffs: Fewer transistors -> smaller gates, esp. for large number of inputs less capacitative load on gates that drive inputs larger power consumption less noise margin (VOL > 0) additional design considerations due to ratioed logic Passive Pullup Device: P-Transistor OUT Pulldo w n Network 6 / 3 / 2 15 291

17. Rationed Logic for Pseudo-nmos Approach: Assume VOUT=VOL =0.25*VDD Assume 1 pulldown transistor is on Equate currents in p, n transistors Solve for ratio between sizes of p, n transistors to get these conditions n e c essa r y f or – Furth e r c a l cul a ti ons series connections I dn  I pn 1 k' W n n L n g s , n tn  2 V  V  2  1 k' W p p L p g s , p t p d s , p d s , p 2  V  V  V  V 2   (EQ 3  21) 2 W p Wn Ln L p  3.9 (EQ 3  22)  Assu min g V DD  3.3V I dp OUT Pulldo w n Network I dn 6 / 3 / 2 15 292

18. DCVS Logic DCVS - Differential Cascode Voltage Switch Differential inputs, outputs Two pulldown networks Tradeoffs Lower capacitative loading than static CMOS No ratioed logic needed Low static power consumption More transistors More signals to route between gates OUT P u ll d o w n Network OUT’ OUT’ P u ll d o w n Network OUT A B C 6 / 3 / 2 15 293 A’ B’ C’

19. Pulldo w n Network C S  A B C Dynamic Logic Key idea: Two-step operation – precharge - charge CS to logic high  – evaluate - conditionally discharge CS Control - precharge clock f Storage Node Storage C a p acita n ce P r ec h arge S i g n al Precharge 6 / 3 / 2 15 294 E v a lua te Precharge

20. Domino Logic Key idea: dynamic gate + inverter Cascaded gates - “monotonically increasing”   C S Pulldo w n Network B C  in4 x1 x2 x3 6 / 3 / 2 15 295

21. 6 / 3 / 2 15 296 Domino Logic Tradeoffs Fewer transistors -> smaller gates Lower power consumption than pseudo-nmos Clocking required Logic not complete (AND, OR, but no NOT)