HDL (hardware description language) presentation

This presentation is about the Languages used to program the hardware devices like electronic circuits including PAL, GAL devices etc.

1. Topic: HDL Saggar Farid Rollno:21 Umar Abid Rollno:35 Hassan Rasheed Rollno:5

2. What is HDL? In  electronics , a hardware description language or HDL is a specialized  computer language  used to program the structure, design and operation of  electronic circuits , and most commonly, digital logic  circuits.

3. What is Logic simulation? Simulation allows an HDL description of a design (called a model) to pass  design verification , an important milestone that validates the design's intended function (specification) against the code implementation in the HDL description . The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design Example: Work Bench Software

4. Functional verification: Histrocially,design verification was a laborious, repetitive loop of writing and running simulation  test cases  against the design under test which takes much time to verify. The  EDA  industry developed the  Property Specification Language . A property or properties can be proven true or false using formal mathematical methods.

5. Types of hdl VHDL Verilog HDL

6. VHDL VHDL ( V Hardware Description Language ) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits Advantage: VHDL is a dataflow language , unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time.

7. VErilog hdl Hardware description languages such as Verilog differ from software  programming languages  because they include ways of describing the propagation of time and signal dependencies (sensitivity). Now a day there is no use of verilog HDL.

8. HDL MODELS OF COMBINATIONAL CIRCUITS The module is the basic building b loak f0r modeling hardware with the Verilog HDL . The logic of a module can be described in any one (or a combination) of the following modeling styles Gate-level modeling Dataflow modeling Behavioral modelings

9. GATE LEVEL MODELING: A logic network can be modeled using continuous assignments or switches and logic gates. Gates and continuous assignments serve different modeling purposes and it is important to appreciate the differences between them in order to achieve the right balance between accuracy and efficiency in Verilog -XL

10. DATA FLOW MODELING: Dataflow modeling provides a powerful way to implement a design. Verilog allows a design processes data rather than instantiation of individual gates. Dataflow modeling has become a popular design approach as logic synthesis tools have become sophisticated. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow.

11. Behavioral Modeling: Verilog behavioral models contain procedural statements that control the simulation and manipulate variables of the data types previously described. These statements are contained within procedures. Each procedure has an activity flow associated with it.

12. Questions???