Ids vs Vds relation in MOSFET VLSI Design.pptx

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1. MOS diagrams P- Sub p- ,n- lightly doped P+,n+ heavily dopde p,n moderately doped P substrate N+ N+ metal Oxide Polysilicon nMOS enhancement mode Vgs > Vth holes Electrons strate e- ,e- Vds> (Vgs- Vth) Ids> P. Bujjibabu, Associate Professor, ECE 5/15/2023 VLSI Design Unit II 1

2. Summary of normal conduction characteristics: Cut- off : accumulation, Ids is essentially zero. Non-saturated : weak inversion, Ids dependent on both Vgs and Vds . Saturated : strong inversion, Ids is ideally independent of V ds. Region NMOS Non-saturation/ Triode V DS < V DS (sat) I  k ' W  ( V  V ) V  1 V 2  D n L   GS TN DS 2 DS   R  V DS DSon I D Saturation/ Pinch- off V DS > V DS (sat) k '  W  2 I D  n   [ V GS  V TN ] 2  L  Transition between triode and pinch- off V DS (sat) = V GS - V TN Enhancement Mode V TN > V, I D ≥ mA, I D = I S , I G = mA VLSI Design Unit II 5/15/2023 7

3. 1. Ids vs Vds derivation A voltage on the gate, Vgs , induces a charge in the channel between source and drain which may then caused electron to move from source to drain under the influence of electric field created by drain voltage Vds. Since the charge induced is dependent on the gate - to- source voltage Vgs, then the Ids is dependent on both Vgs and Vds . Consider the structure, as shown in figure below, in which electron will flow from source - to- drain 8

4. The drain to source current Ids is I Where But velocity of moving particle is between drain and the source , and hence electron velocity There fore which is then given by  Charge induced in a channel (Q c ) ds - sd  I sd Electron transit time(  ) Electron velocity (v)  Length of the channel(L) sd  v   n E ds with an effective field developed L V ds E ds  L V ds v   n L V ds n  L sd   n ds  V sd L 2   where  n  650 / v -s and  p  240 / v - s   9

5. The Non- Saturation region: Where Qo is the charge per unit area which is given by and Eg is average electric field in the gate to channel and is given by The total induced charge (Qc) in the channel is then given by Q c  Q WL Q  E g  ins  V D D D V ds gs t g E g      V  V      V   V ds        G 2 2  ins is the relative permittivity of the insulation  is the absolute permittivity Vg is the effective gate voltage = Vgs- Vt Vds/2 is the average voltage at drain terminal Vt is the threshold voltage W is the width of the MOS transistor L is the length of the MOS transistor V G is the gate voltage under Vds D is the thickness of the gate oxide layer 5/15/2023 VLSI Design Unit II 10

6. The total induced charge (Qc) in the channel is then given by Thus the drain - to - source current is given by V ds gs t      D   V  V   2 ins Q c    WL . gs t sd c n V ds Q I ds  2 ins L 2   WL .      D   V ds   V  V    L 2 1 2 n ds ds gs t ins V I ds .  V      D   V  V      WL . ds t gs n ds V D 2 L 2 ins  . V ds     1   V  V   I  WL .  .   ds t gs g n ds V 2 2  . V ds      V   I  C .  . 1   V  C   A D or or VLSI Design U n L it II or 5/15/2023 11

7. In other words the same current is also given by The Saturation region: Saturation begins when ds gs t ds V 2 n  . V ds    L   I  C  . W   V  V   ds gs t ds V 2  . V ds     I  K . W   V  V    L V ds  V gs  V t 2 2       . V ds 2  V ds L  W   I ds  K .            2 2 2 ds V L  W    K . L  W  2 V ds 2  V ds 2  I ds  K . 2 2 2  V gs  V t  2     V  I ds   .  ds    . or or 12

8. V- I characteristics of nMOS The parameters that effect the magnitude of Ids are: The distance between source and drain (channel length). The channel width. The threshold voltage. The thickness of the gate oxide layer. The dielectric constant of the gate insulator. The carrier (electron or hole) mobility. ds t gs n ds V D 2 L 1 2 ins  . V ds       V  V   I  WL .  .   5/15/2023 VLSI Design Unit II 13

9. Aditya Engineering Aspects of MOS Transistor: Threshold voltage: Vt The MOSFET conducts no current between its source and drain terminals unless V GS is greater than V th . Increasing the gate-to- source voltage above and beyond V th will not affect the surface potential and the depletion region depth. The gate to source voltage, for which the concentration of electrons under the gate is equal to the concentration of holes in the p- sub far from the gate called the THRESHOLD VOLTAGE (Vt h = Vgs) and is given by V th  V FB  2  F ox C 2  s qN A (2  F  V SB ) Flat band voltage https://ecee.colorado.edu/~bart/book/book/chapter7/ch7_4.htm Lot more to know about the Vt. If you wish, go through the link 5/15/2023 14 VLSI Design Unit II From equations, threshold voltage may be varied by changing: The doping concentration (N A ). The oxide capacitance (C ox ). Surface state charge (Q fc ).

10. GS TH m n ox L g   C W  V  V  For a short- channel MOSFET: g m  v sat WC ox Key factors influencing the MOS Performance Aspects of MOS Transistor: T ran s conduc t ance, gm In most MOSFET applications, an input signal is the gate voltage V G and the output is the drain current I d . The ability of MOSFET to amplify the signal is given by the output current /input voltage ratio, the Transconductance, Transconductance (gm) is a measure of how much drain current changes wrt the gate voltage. For amplifier applications, the MOSFET is usually operating in the saturation region. For a long- channel MOSFET: 5/15/2023 VLSI Design Unit II 16

11. The output conductance of a MOS device is defined as the ratio between the change in output current to the change in output voltage. The output conductance in non saturation is given by and decreases with increase in Vds ( gds is for saturation region ). V gs  Constant ds ds  V   I ds g Aspects of MOS Transistor: Output Co n d u cta nce, gds gs t ds ds n ox L  V  V g   C W  V  Aspects of MOS Transistor: figure of merit w o Figure of merit is used obtain the frequency response characteristics of a MOS device in presence of AC source at gate. r s & r d are ignored and all drops are zero The figure of merit is given by L 2 Cox WL L g n ox gs t m C g   w   n  V gs  V t   C W  V  V  5/15/2023 VLSI Design Unit II 17

12. MOSFET Pass Characteristics 5/15/2023 VLSI Design Unit II 18

13. cMOS inverter Vdd Vin PD n/w PU n/w Vout When Vin =0, then pMOS transistor(PU) is ON and nMOS transistor is off Vdd( logic 1) When Vin =1, then T3 is ON(T4 OFF) implies T1 ON (T2 OFF) and hence Vout= 0( logic 0) Good with large driving capability. Vss 0.5Vdd Vdd Vout Vin Vinv 0.5Vdd Vdd Vout Vin Vinv 5/15/2023 VLSI Design Unit II 24

14. Beta Ratios Region C is the most important region. A small change in the input voltage, V in , results in a LARGE change in the output voltage, V out . This behavior describes an amplifier, the input is amplified at the output. The amplification is termed transistor gain, which is given by beta. Both the n and p- channel transistors have a beta. their ratio will change the characteristics of the output curve.  Va 5/ r 1 y 5/ i 2 n 02 g 3 VLSI Design Unit II 28

15. 5/15/2023 VLSI Design Unit II 29

16. Pull up to pull down ratio The transfer characteristics and Vinv can be shifted by varying the Zpu/Zpd As shown in figure, an inverter is driven by another similar inverter Consider the depletion mode transistor as pull up , for which Vgs=0 under all conditions and meeting the requirement Vin=Vout= Vinv Vin 1 Vin 2 V out 1 V out2 V DD V gs =0 V gs = V inv I ds1 I ds2 Case- I Fig: Inverter driven by another inverter 5/15/2023 VLSI Design Unit II 31

17. Pull up to pull down ratio Let us consider at Vg=Vin=Vinv=0.5V DD, both the transistors in an inverter are in saturation with a drain current of;  2 In depletion mode tr(PUN) , the drain current can be re written as and the current in the enhancement mode tr(PDN) , is   2 t  I  K gs W   V  V L ds   2   2    V td I  K L W pu pu ds V DD V gs =0 V gs = V inv I ds1 I ds2  2   2   V inv  V t  I  K L W pd pd ds 5/15/2023 VLSI Design Unit II 32

18. Pull up to pull down ratio In saturation, current in both the transistors are equal and hence This is pull up to pull down ratio of inverter driven by another inverter 2    2     2  2  W L pd W   V td  V inv  V t pu L pu pd   pd pd pu pu td pu t inv pd W and Z W Z Z  L pd  L pu  V  V     V  ;Since, Z 1 1 2 2 2 2 2 2 t inv /  V  V  td    V  pd pu td    V   t inv  V  V  pd pu Z Z Z Z V td t   0.6 V V  0.2 V here; V inv  0.5 V 1  4  Z pu Z pd 5/15/2023 VLSI Design Unit II 33

19. Pull up to pull down ratio of ….. through one or more PTs Let us consider the arrangement shown in fig. input to inverter 2 is from output of inverter 1, but through the series of nMOS transistors called Pass Transistors Case- II Fig: Inverter driven by another inverter through one or more Pass Transistors V out 1 V out2 Vin 1 0V V DD V gs =0 V gs = V DD I ds1 I ds2 V DD V gs =0 V gs = V DD - V tp I ds1 I ds2 (VDD- Vt1)- Vt2 - Vtp V DD V V DD - V t1 or VDD DD V DD Vin 2 ~ 1 1 <V DD V DD V tp 5/15/2023 VLSI Design Unit II 34

20. We are now concerned that connection of pass transistors in series will degrade the logic 1 level into inverter 2 so that the output will not be a proper logic level. So as given in fig. input to inverter 2 is reduced by threshold voltage of series of nMOS pass transistors. For this reduced voltage at input to inverter 2, we must get out the same as would be the output of inverter 1. R 1 Depletion mode Vout1=I 1 R 1 I 1 T 1 Enhancement mode T 2 Vin=V DD Fig: Inverter 1 with Vgs=Vin= V DD R 2 Vout2=I 2 R 2 I 2 Enhancement mode T 2 Vin=V DD - Vtp T 1 Depletion mode Fig: Inverter 2 with Vgs=Vin= V DD - Vtp V DD V gs =0 V gs = V DD I ds1 I ds2 V DD V gs =0 V gs = V DD - V tp I ds1 I ds2 5/15/2023 VLSI Design Unit II 35

21. If the input is at VDD, then the pd transistor T2 is conducting but with a low voltage across it ,and is said to be linear mode or resistive mode represented by R1 shown in fig. But, Pu transistor T1 is in saturation and is said to be constant current source. For the Pd transistor, ; here Vgs=Vdd For the Pu transistor, • ; here Vgs=0 2 W pd 1  V ds 1  I ds  K L  ( V gs  V t )   V ds 1 pd 1            1   1 1 ds 1 2 DD t pd 1 ds V  ( V  V )  L pd 1 K W I  V ds 1  R 1  here Vds1 very small and hence neglected      (1)  pd 1  ds 1  V t )   ( V DD K I ds V 1  R 1   Z Pull up to pull down ration Derivation V W pd 1    I ds  K  ( V DD  V t )  ds 1  V ds 1 L pd 1  2  L pu 1   2 W  ( V  V ) 2  pu 1  gs t ds I  K    2 5/15/2023 VLSI Design Unit II 36 W pu 1  (0  V td ) 2   I ds  K  L pu 1     

22. 1 2 pu 1  (  V td ) 2  I 1  I ds  K Z        (2)   1 1 Now Vout 1  I R     V t   V DD  td   Z pu 1   K K X 1 1 Z pd 1  2 1  (  V ) 2  1 2      (A) ) 2    td   V t   V DD  (  V Z pu 1   Z pd 1 V out 1 2       1     (3) Now consider inverter 2 with input (V DD  V tp ) t tp DD pd 2 ds ( V  V  V )   1 Z K I  V ds 2  R 2 1  (  V td ) 2  and I 2  I ds  K Z  pu 2       (4)   Now Vout 2  I 2 R 2      V tp  V t     V DD K  td  X  K 1 1 2 1  (  V Z pd 2  ) 2  Z pu 2  1 2      (B) ) 2     td      V DD  V tp  V t    (  V Z pu 2   Z pd 2 V out 2 And hence, 5/15/2023 VLSI Design Unit II 37

23. If inverter 2 is to have the same output voltage under these conditions as inverter 1,then Vout1= Vout2. ie… I1R1=I2R2 Modifying the above equation, will give; Which leads For an inverter driven by another inverter is with and inverter driven by another inverter through one or more Pass Transistor logic with is desirable to have proper logic at o/p with expected amount of shift                  td td  V tp  V t      V DD Z Z 1 2 (  V ) 1 2  V t  (  V ) 2 Z pu 2  pd 2 2 Z pu 1    V DD pd 1  V  V    V Z Z ( V DD  V t ) pd 1   DD tp t    Z pu 1  pd 2 Z pu 2 at V t  0.2 V DD and V tp  0.3 V DD  4  2   8 1 1 pd 2 Z Z pu 2 1  4 Z pd Z pu 1  8 Z pd Z pu 38 5/15/2023 VLSI Design Unit II

24. Switch logic and gate logic Switch logic is based on the pass transistor (PTL)or on the transmission gate logic(TGL). This approach is fast for small arrays and takes no static current from the supply rails. Hence power dissipation is small since current flows on switching only. Switch (or pass transistor) logic is similar to logic arrays based on relay contacts The designer can implement logics with expected features. 5/15/2023 VLSI Design Unit II 39 AND gate in PTL

25. Switch logic and gate logic 5/15/2023 VLSI Design Unit II 40 Ex Or gate in PT Logic

26. Vin Vout Vdd Vss Vin Vout Vdd Vss 5/15/2023 VLSI Design Unit III P. Bujjibabu, Associate Professor, ECE 41

27. Series/Parallel Equivalent Circuits Scale both W and L – no effective change in W/L – increases gate capacitance inputs must be at same value/voltage Series Transistors – increases effective L Parallel Transistors – increases effective W effective  ½  effective  2   =  Cox (W/L) 5/15/2023 VLSI Design Unit II 42

28. Consider above cited books for reference only and you may get more information from some other books and websites Collect notes from your subject Teacher, if interested. Note: http://emicroelectronics.free.fr/onlineCourses/VLSI/toc.html http://ece- research.unm.edu/jimp/vlsi/slides/c1_itrs.pdf http://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/HTML/HOMEPG.HTM https://www.tutorialspoint.com/vlsi_design/vlsi_design_useful_resources.htm https://www.southampton.ac.uk/~bim/notes/cad/ http://www.uta.edu/ronc/4345sp02/lectures/ http://www.ece.utep.edu/courses/web5392/Lab_7.html http://www.ece.utep.edu/courses/web5392/Notes.html http://www.ittc.ku.edu/~jstiles/312/handouts/ https://www.mepits.com/tutorial/384/vlsi/steps-for- ic-manufacturing Useful Web links: P. Bujjibabu, Associate Professor, ECE 5/15/2023 VLSI Design Unit II 43