Instruction Execution in Computer Organization.pptx

The complete execution of an instruction involves the fetch-decode-execute cycle, where the processor first fetches the instruction from memory using the program counter (PC), then decodes it to understand the operation and required data, and finally executes the instruction by performing the specified action, such as arithmetic/logic operations or data transfers, before fetching the next instruction.

1. SNS COLLEGE OF TECHNOLOGY An Autonomous Institution Coimbatore-35 Department of Computer Science & Engineering 23ITT202 – Computer Organization & Architecture II B.E CSE / III SEMESTER UNIT III : Processor & Pipelining Topic 1 : Instruction Execution

2. Let’s Recall !! 08-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT Register Transfer Notation (RTN) describes the transfer from one location in computer to another . Possible locations: memory locations, processor registers 2 /30 R2 ← [LOC]

3. Topics for discussion Instruction Execution Execution of Complete Instruction 08-10-2025 3 /30 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

4. Brai nStorm !! 08-10-2025 4/30 Guess 2.What is Execution? What is Instruction? COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

5. The Tale of the Tiny Kitchen: How a Computer Follows a Recipe DT-Empathize 08-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 5 /30 With all the available Items could you pls make " Peanut Butter Sandwich " Program:  The full recipe (Make a Sandwich). Instruction:  A single step in the recipe (GET BREAD). Fetch:  Getting the step. Decode:  Understanding the step. Execute:  Doing the step.

6. Instruction Execution (1/3) 1) Fetch Phase – 2)Execute Phase – –Decode instruction in IR –Perform the operation(s) IR PC = [[PC]] [PC]+4 •Fetch the contents of the memory location pointed to by PC, and load into IR •Incrementthecontents of PC by 4. –Why 4?Instruction is32 bits (4B) and memory is byte addressable. lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 6 /30 08-10-2025

7. Instruction Execution (2/3) 1) Fetch Phase – 2)Execute Phase – –Decode instruction in IR –Perform the operation(s) IR PC = [[PC]] [PC]+4 •Fetch the contents of the memory location pointed toby PC, and load into IR •Increment the contents of PC by 4. –Why 4?Instruction is 32 bits (4B) and memory is byte addressable. lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 7 /30

8. Instruction Execution (3/3) 1) Fetch Phase – 2)Execute Phase – –Decode instruction in IR –Perform the operation(s) IR PC = PC+4 [[PC]] •Fetch the contents of the memory location pointed toby PC, and load into IR • Incrementthe contents of PC by 4. –Why 4?Instruction is32 bits (4B) and memory is byte addressable. lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 8 /30

9. Instruction Execution: Execute Phase •An instruction can be executed by performing one or more of the following operation(s): 1)Transfer data from a register to another register or to the ALU 2)Perform arithmetic (or logic) operations and store the result into the special register Z 3)Load content of a memory location to a register 4)Store content of a register to a memory location • Sequence of Control Steps : Describes how these operations are performed in processor step by step. COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 9 /30 DT-Define

10. 1) Register Transfer Input and output of register Ri are controlled by switches ( ): –Ri-in : Allow data to be transferred into Ri –Ri-out :Allow data to be transferred out from Ri lines Ri Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … Ri-in Ri-out COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 10 /30 DT- Ideate

11. 1) Register Transfer (Cont’d) •Ex:   R1-out, R3-in •Recall: R3 = [R1] Sequence of Steps:  Clock 2: •Reset R1-out to 0 •Reset R3-in to 0 Clock Cycle Clock Clock 1:R1-out, R3-in •Set R1-out to 1 •Set R3-in to 1 •Set all others to 0 Note: Only state“sets”forshort . lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 11 /30

12. Let’s Solve •What is the sequence of steps for the following operation? R1 [R3] lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 12 /30

13. lines 2) Arithmetic or Logic Operation Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internalprocessor bus Control signals … Select XOR Carry in n-1 … … R1-out, Y-in Select-Y, R2-out, B-in, Add, Z-in Z-out, R3-in • ALU :A circuit without storage to manipulate data. – : #4 or register Y Sequence of Steps: – – :from A&B : Perform operation R3 : to register Z Two inputs ALU One output • • : Any other register A B •Ex: [R1] + [R2]    COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 13 /30 DT- Prototype

14.    R1-out, Y-in Select-Y R2-out, B-in, Add , Z-in Z-out, R3-in 2) Arithmetic or Logic Operation ( Contd ) •Ex: R3 = [R1]+ [R2] COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 14 /30

15. What is the sequence of steps for the following operation? R6 = [R4] – [R5] lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … Find out COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 15 /30

16. Recall: Processor-Memory Interface • Data transferring takesplace through M A R andM D R. – – : Memory Address Register : Memory Data Register MAR MDR M D R Control lines ( R / W , MFC, etc.) k -bit address bus (byte-addressable) n -bit Up to 2k addressable memory locations Word length = n bits Processor M A R Memory data bus (unit: word ) *MFC(MemoryFunction Completed): Indicating the requested operation has been completed. COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 16 /30

17. 3) Loading Word from Memory MDR-in E MDR-out E MAR MDR MDR-in MDR-out MAR-in E xternal memory bus ( data lines ) E xternal memory bus ( address lines ) Internal processorbus Register • MAR :MemoryAddress Register – Uni-directional bus( ) –Connect to the address lines directly –Bi-directional bus connections to buses are all controlled by switches ( ). :Memory Data • MDR 08-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 17 /30

18. WaitMFC •Ex: R1-out, MAR-in, Read MDR-out, R2-in MovR2, (R1) Sequenceof Steps: (start to load a word from memory) (wait until the loading is completed) MDR-inE, Z PC R/W MFC (Control lines) MAR Addr lines MDR Data lines Y Constant 4 MUX Add Sub A B ALU R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … 3) Loading Word from Memory (Cont’d) COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 18 /30

19. Find the Steps What is the sequence of steps for the following operation? Mov R4,(R3) lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 19 /30

20. 4) Storing Word to Memory Select XOR Carry in Z PC R/W MFC (Control lines) MAR Addr lines MDR Data lines Y Constant 4 MUX Add Sub A B ALU R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … … Write MDR-outE, WaitMFC •This operation is similar to the previous one. •Ex: Mov(R1), R2 Sequence of Steps:  R1-out, MAR-in   R2-out,MDR-in, (starttostorea word into memory) (wait until the storing is completed) COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 20 /30

21. Find the Steps What is the sequence of steps for the following operation? Mov (R3), R4 lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 21 /30

22. Loading Word vs Storing Word R2-in Ex:  R1-out, MAR-in, Read MDR- inE , Wait MFC Ex:  R1-out, MAR-in  R2-out, , , WaitMFC MDR-out , Loading Word MovR2, (R1) Write MDR-outE Storing Word Mov(R1), R2    MDR-in COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 22 /30

23. Revisit: Fetch Phase of steps for the fetch phase with the highest parallelism? • FetchPhase :The firstphase of machine instruction execution – lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … IR [[PC]] •Increment the contents of PC by 4 •Fetch the instruction from the memory location pointed to by PC, and load it into IR – PC [PC]+4 • What is the sequence COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 23 /30

24. Fetch Phase (1/3) MDR-out, IR-in MDR-inE, WaitMFC Z-out, PC-in, Y-in •Ex: Fetch Phase Sequence of Steps:  PC-out, MAR-in, Read Select-4, B-in, Z-in, Add   –Increment PC – Y-in is for branch –Fetch the instruction in parallel Select XOR Carry in Z Y Constant 4 MUX Add Sub A ALU B PC R/W MFC (Control lines) MAR Addr lines MDR R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 24 /30

25. Fetch Phase (2/3) MDR-out, IR-in MDR-inE, WaitMFC Z-out, PC-in, Y-in • Ex: Fetch Phase Sequence of Steps:  PC-out, MAR-in, Read Select-4, B-in, Z-in, Add   –Y-inisfor branch (discuss later). –Fetchthe instruction –Increment PCinparallel. Select XOR Carry in Z Y Constant 4 MUX Add Sub A ALU B PC R/W MFC (Control lines) MAR Addr lines MDR R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … … 08-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 25 /30

26. Fetch Phase (3/3) MDR-out, IR-in MDR-inE, WaitMFC Z-out, PC-in, Y-in •Ex: Fetch Phase Sequence of Steps:  PC-out, MAR-in, Read Select-4, B-in, Z-in, Add   –Y-inisfor branch (discuss later). –Fetchthe instruction –Increment Pc in parallel. Select XOR Carry in Z Y Constant 4 MUX Add Sub A ALU B PC R/W MFC (Control lines) MAR Addr lines MDR R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 26 /30

27. Observations and Insights •Independent operations imply the possibility of performing some steps in parallel . •During memory access, processor waits for MFC . •The internal processor bus and the external memory bus can be operated independently (concurrently). – Since the separation provided by MAR and MDR. – E.g.,memory access and PC increment, instruction – There is NOTHING TO DO BUT WAIT for few cycles. – decoding and reading source register Question: Any way to improve this situation? COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 08-10-2025 27 /30

28. Let’s summarize 08-10-2025 28 /30 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

29. References Carl Hamacher , Zvonko Vranesic and Safwat Zaky ,“Computer Organization”, McGraw-Hill,5th Edition 2014. 08-10-2025 29 /30 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

30. 08-10-2025 30 /30 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT