Interfacing technique with 8085- ADC[0808]

ADC 0808

1. INTERFACING TECHNIQUE WITH 8085 ANALOG TO DIGITAL CONVERTER[0808/0809] GUHAN K DEPARTMENT OF EEE JEPPIAAR SRR ENGINEERING COLLEGE CHENNAI-603103

2. ADC0808-N

3. DEFINITION An electronic integrated circuit which transforms a signal from analog(continues) to digital(discrete) form Analog signals are directly measurable quantities Digital signals only have two states for digital computer we refer to binary states, 0 and 1 The heart of computer-based data acquisition is usually the analog to digital converter

4. Basically this device is digital volt meter Digital Systems require discrète digital data Digital computers require signals to be in digital form whereas most instrumentation transducers have an output signal in analogue form. ADC conversion is therefore required at the interface between analogue transducers and the digital computer

5. Microprocessors can only perform complex processing on digitized signals ADC Provides a link between the analog world of transducers and the digital world of signal processing and data handling.

6. There are many different types of analog to digital converters Each offers something in the way of Speed Cost Power dissipation complexity Counter type Successive approximation There are many types such as flash type and sigma-delta but we will cover these two types

7. ADC 0808 data acquisition component is a monolithic CMOS device with 8 channel multiplexer and microprocessor compatible control logic. The 8 channel multiplexer can directly access any of 8 single ended analog signal

8. PIN DIAGRAM OF IC ADC0808

9. Selected Analog Channel Address Line C B A IN0 L L L IN1 L L H IN2 L H L IN3 L H H IN4 H L L IN5 H L H IN6 H H L IN7 H H H ADDRESS SELECT LINE Because the chip has an 8 channel multiplexer there are three address select lines: A, B, and C. C is the most significant bit and A is the least . See table 1 for details

10. ALE [ADDRESS LATCH ENABLE] ALE is required to load the selected address lines into the ADC. Once loaded the multiplexer sends the appropriate channel to the converter on the chip. The ALE should be pulsed for at least 100ns in order for the addresses to get loaded properly. As with all control signals it is required to have an input value of Vcc - 1.5 up to 15V for a high and 1.5V down to -0.3V for a low.

11. CLOCK The clock signal is required to cycle through the comparator stages to do the conversion. There are 8, 8 clock cycle periods required in order to complete an entire conversion. This means that an entire conversion takes at least 64 clock cycles. The clock should conform to the same  range as all other control signals.  The maximum frequence of the clock is 1.2MHz  

12. START The purpose of the start signal is two fold. On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated. Like the ALE pulse the minimum pulse width is 100ns. The signal can be tie to the ALE signal when the clock frequency is below 500kHz.   Note that it can take up to 2.5 microseconds for this to occur.  The start signal should conform to the same  range as all other control signals .

13. OE [OUTPUT ENABLE] The Output Enable signal causes the ADC to actually output the digital values on the output lines. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled. In this implementation the OE signal is pulsed high one clock cycle after the  EOC  signal goes high and remains high until the data is safely stored into the desired register in the FPGA. The OE signal should conform to the same  range as all the other control signals .

14. EOC [END OF CONVERSION] The signal goes low once a conversion is initiated by the start signal and remains low until a conversion is complete.

15. Pin Number Label Input/Output Description Required Note: All control signals should have a high voltage from Vcc - 1.5 to 15V and a low voltage from 1.5V to -0.3V. 1 IN3 Input Analog data in. It is selected as channel 3 by the multiplexer. CBA = 011. No, can tie to ground 2 IN4 Input Analog data in. It is on channel 4 of the multiplexer. CBA = 100. No, can tie to ground 3 IN5 Input Analog data on channel 5 of the multiplexer. CBA = 101. No, can tie to ground 4 IN6 Input Analog data on channel 6 of the multiplexer. CBA = 110. No, can tie to ground 5 IN7 Input Analog data on channel 7 of the multiplexer. CBA = 111. No, can tie to ground 6 Start Input It is a control signal from the FPGA, which tells the converter when to start a conversion. It is a pulse of at least 100ns in width. Yes 7 EOC Output Signal from the ADC. It goes low when a conversion is started and high at the end of a conversion. Users can look for a rising edge transition. Yes 8 2 -5 Output This is a bit of the digital converted output. Where 2 -8  is the LSB and 2  -1  is the MSB. No

16. 9 Output Enable Input Control signal for FPGA that turns the output of the ADC on while high. Useful for handshaking. No, can tie to Vcc. 10 Clock Input Clock signal from FPGA. Max 1.2MHz. Yes 11 Vcc Input Power to the chip. Range 4.5V to 6.0V DC. Yes 12 V REF (+) Input Top rail of Reference voltage. The voltage level that, when received as an input, will output "11111111" to the FPGA. Max Value Vcc + 0.1V Yes 13 GND Input Ground. 0V Yes 14 2 -7 Output This is a bit of the digital converted output. Where 2 -8  is the LSB and 2  -1  is the MSB. No 15 2 -6 Output This is a bit of the digital converted output. Where 2 -8  is the LSB and 2  -1  is the MSB. No 16 V REF (-) Input Bottom rail of Reference voltage. The voltage level that, when received as an input, will output "00000000" to the FPGA. Min Value -0.1V Yes

17. 17 2 -8 Output This is a bit of the digital converted output. 2 -8  is the LSB. No 18 2 -4 Output This is a bit of the digital converted output. Where 2 -8  is the LSB and 2  -1  is the MSB. No 19 2 -3 Output This is a bit of the digital converted output. Where 2 -8  is the LSB and 2  -1  is the MSB. No 20 2 -2 Output This is a bit of the digital converted output. Where 2 -8  is the LSB and 2  -1  is the MSB. No 21 2 -1 Output This is a bit of the digital converted output. 2  -1  is the MSB. No 22 ALE Input  Control signal from FPGA. This should be a pulse from the FPGA sent when the address is ready to be loaded into the ADC. The minimum pulse width is 100ns. It can be tied to the Start line if the clock is operated under 500kHz. Yes

18. 23 ADD C Input Control signal from FPGA. This is an address select line for the multiplexer. It is the MSB of the select lines. No, can tie to ground 24 ADD B Input Control signal from FPGA. This is an address select line for the multiplexer. It is the Second bit of the select lines. No, can tie to ground 25 ADD A Input Control signal from FPGA. This is an address select line for the multiplexer. It is the LSB of the select lines. No, can tie to ground 26 IN0 Input Analog data on channel 0 of the multiplexer. CBA = 000. No, can tie to ground 27 IN1 Input Analog data on channel 1 of the multiplexer. CBA = 001. No, can tie to ground 28 IN2 Input Analog data on channel 2 of the multiplexer. CBA = 010. No, can tie to ground.

19. BLOCK DIAGRAM OF IC ADC0808

20. BLOCK DIAGRAM OF ADC[0800]

21. INTERFACING BLOCK WITH 8085

22. FEATURES OF 0808/0809 28 PIN Resolution-8 bits High accuracy High conversion speed[100ms at 640kHz] 8-channel multiplexer with latched control logic Output meet TTL voltage level specifications Latched Tri-state output Clock Frequency 10kHz to 1280kHz