INTERRUPT CONTROLLER 8259 MICROPROCESSOR

Microprocessors & Microcontrollers: Interrupt controller 8259; The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and 8086 there are five hardware interrupts and two hardware interrupts respectively. Bu adding 8259, we can increase the interrupt handling capability. This chip combines the multi-interrupt input source to single interrupt output. This provides 8-interrupts from IR0 to IR7. Let us see some features of this microprocessor.

This chip is designed for 8085 and 8086.

It can be programmed either in edge triggered, or in level triggered mode

We can mask individual bits of Interrupt Request Register.

By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines

Clock cycle is not needed.
8259 microprocessor can be programmed according to given interrupts condition and it can be provided either with level or edge-triggered interrupt level.
It can be programmed to either work in 8085 or in 8086 microprocessors.
Individual interrupt bits can be masked.
By cascading Nine 8259’s in Master-Slave Configuration we can handle up to 64 interrupt pins.
It contains 3 registers commonly known as ISR, IRR, IMR & there is 1 priority resolver (PR).


Interrupt Request Register (IRR): It stores those bits which are requested for their interrupt services.
Interrupt Service Register (ISR): It stores the interrupt levels which is currently being served.
Interrupt Mask Register (IMR): It stores interrupt levels that have to be masked. These interrupt levels are already accepted by the 8259 microprocessor.
Priority Resolver (PR): It examines all the 3 registers and sets the priority of interrupts and sets the interrupt levels in ISR which has the highest priority and the rest of the interrupt bit is IRR which is already accepted.

SP/EN (low active pin): If its value is 1 it works in master mode & if its value=e is 0 then it works in slave mode.

Cascade Buffer: It is used to cascade more number of Programmable Interrupt Controller to increase the interrupts handling capability up to 64 levels.

Advantages:
Interrupt management: The 8259 microprocessor is a specialized chip that is dedicated to managing interrupts, which can help to improve system performance and reduce the workload on the main CPU.

Programmability: The 8259 microprocessor is programmable, which means that it can be customized to handle specific types of interrupts and to prioritize different interrupt requests.

Compatibility: The 8259 microprocessor is compatible with a wide range of microprocessors, making it a popular choice for interrupt management in many different systems.

Multiple interrupt inputs: The 8259 microprocessor can handle multiple interrupt inputs, which makes it a useful peripheral for managing complex systems with multiple devices.

Ease of use: The 8259 microprocessor includes simple interface pins and registers, making it relatively easy to use and program.

1. INTERRUPT CONTROLLER 8259 Presentation by: tanishka hira(IGDTUW)

2. Intel 8259 Intel 8259 is a  Programmable Interrupt Controller (PIC) . There are 5 hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086 microprocessors respectively. But by connecting Intel 8259 with these microprocessors, we can increase their interrupt handling capability. This chip combines the multi-interrupt input source to single interrupt output. This provides 8-interrupts from IR0 to IR7. INTERRUPT CONTROLLER 8259 2

3. FEATURES OF INTEL 8259 PIC INTERRUPT CONTROLLER 8259 3 Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor. It can be programmed either in level triggered or in edge triggered interrupt level. We can mask individual bits of interrupt request register. We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259 PICs. Clock cycle is not required.

4. PIN DIAGRAM OF 8259 INTERRUPT CONTROLLER 8259 4

5. BLOCK DIAGRAM OF 8259 INTERRUPT CONTROLLER 8259 5

6. About each BLOCK Block : Description Data Bus Buffer : This block is used to communicate between 8259 and 8085/8086 by acting as buffer. It takes the control word from 8085/8086 and send it to the 8259. It can send maximum 8-bit at a time. R/W Control Logic : This block works when the value of pin CS is 0. This block is used to flow the data depending upon the inputs of read(RD) and write(WR). Control Logic : It controls the functionality of each block. It has pin called INTR. This is connected to other microprocessors for taking the interrupt request. The INT pin is used to give the output. Interrupt Request Register : It stores all interrupt level that are requesting for interrupt service. Cascade Buffer : To increase number of interrupt pin, we can cascade more number of pins, by using cascade buffer. When we are going to increase the interrupt capability, CSA lines are used to control multiple interrupts. Interrupt Mask Register : It stores interrupt level that will be masked, by storing the masking bits of interrupt level. Priority Resolver : It checks all three registers, and set the priority of the interrupts. Interrupt with the highest priority is set in the ISR register. It also reset the interrupt level which is already been serviced in the IRR. Interrupt Service Register : It stores interrupt level that are currently being execute. INTERRUPT CONTROLLER 8259 6

7. OPERATION MODE OF 8259: Fully nested mode  : It is the default mode of operation of 8259. Here, IR  has the highest priority and IR 7  has the lowest priority. When any interrupt requests occurs then the highest priority interrupt request is serviced first and its vector address is placed on data bus and its corresponding bit in ISR register is set until the processor executes the EOI command before returning the interrupt service routine until the falling of the last INTA’. When the ISR bit is set for an interrupt, then all the equal and lower priority interrupts are masked, but a higher level interrupt request can occur and which will be acknowledged only if the microprocessor interrupt enables flag IF= 1. It is suitable for a single 8259 configuration. Special fully nested mode (SFNM) : This mode is used by master 8259 in a cascaded mode. Its priority structure is fixed and is the same as fully nested mode (i.e. IR  has the highest priority and IR 7  has the lowest priority). In a special fully nested mode, the master will only serve higher priority interrupt from a slave, whose another interrupt is currently in service. Special mask mode(SMM) : In SMM, 8259 enables interrupts of all levels (lower or higher) except the one that is currently in service. Because we are especially masking the request of the priority level of interrupt, which is the same as the current interrupt priority level, therefore it is called special  mask mode . Poll mode : Here the INT pin of 8259 is not used, so, 8259 cannot interrupt the µp. Instead, the µP will provide a poll command to 8259 using OCW 3 . In response, 8259 provides a poll word to the µP. The poll word indicates the highest priority interrupt which needs service from µP. Thereafter, the µP services the interrupt.  INTERRUPT CONTROLLER 8259 INTERRUPT CONTROLLER 8259 7

8. 5 . EOI – (End Of Interrupt) : When the microprocessor acknowledges an interrupt request by sending the first INTA signal, the 8259 sets the corresponding bit in the In Service Register (ISR). This starts the service of the interrupt.  When this bit in the ISR is cleared, then it is known as the end of interrupt (EOI). EOI Modes: 1 . Normal EOI Mode – Here, an EOI command is compulsory. The EOI command is written by the programmer at the end of the ISR. It makes 8259 to reset the bit from ISR. Further EOI command is of two types : i ) Non Specific EOI Command :  Here the programmer doesn’t specify the bit number to be reset in the ISR. 8259 itself resets the highest priority bit from ISR. ii) Specific EOI Command :  Here the programmer determines the bit number to be reset from ISR. 2.  Automatic EOI mode (AEOI) – In this mode, the EOI command is not required. Instead, 8259 will itself clear the corresponding bit from ISR at the end of the 2 nd INTA pulse. 6. Edge and level-triggered mode  : If the LTIM bit of ICW 1  =0 then the edge-triggered interrupt mode is set, otherwise the interrupts are level triggered. 7. Buffered Mode : 8259 sends a buffer enabled signal on the SP’/ EN’ pin when data is placed on the data bus. 8 INTERRUPT CONTROLLER 8259 INTERRUPT CONTROLLER 8259

9. INTEL 8259A Revised version of INTEL 8259

10. The Intel 8259A is indeed a revised version of the original Intel 8259 Programmable Interrupt Controller (PIC). The 8259A was introduced to address some limitations and improve upon the functionality of the original 8259. The 8259A is a programmable interrupt controller (PIC) that works with Intel microprocessors 8085, 8086, and 8088.  The 8259 works with 8-bit processors, while the 8259A works with 8-bit and 16-bit processors. INTERRUPT CONTROLLER 8259 10

11. How is 8259A different from 8259 Improved cascade support for handling more interrupts. Refined initialization process for more setup. Maintains compatibility with 8259. May perform improved performance and reliability. INTERRUPT CONTROLLER 8259 11

12. SOURCES WEBSITES https://www.geeksforgeeks.org/8259-pic-microprocessor/ https://www.tutorialspoint.com/8259-pic-microprocessor/ https://www.youtube.com/watch?v=IAMpcsGDlGo&t=2s/ https://www.geeksforgeeks.org/operating-modes-of-8259-pic/ ThaNK you