Introduction to Built In Self Test (BIST).pdf

VLSI Design- Built In Self Test(BIST)
Prepared by Mrs.V.Femila Savio/AP/ECE

1. Built In Self Test(BIST)
Prepared by
Mrs.V.FemilaSavio/AP/ECE
St.Xavier’sCatholicCollegeofEngineering,Nagercoil

2. Introduction
•Thesetechniquesaddareatothechipforthetest
logic,butreducethetesttimerequiredandthus
canlowertheoverallsystemcost.
•Thisinvolvesusingapseudo-randomsequence
generator(PRSG)toproducetheinputsignalsfora
sectionofcombinationalcircuitryandasignature
analyzertoobservetheoutputsignals.

3. Overview
Fig. Built in Self Test

4. PRSG
•APRSGoflengthnisconstructedfromalinear
feedbackshiftregister(LFSR),whichinturnismade
ofnflip-flopsconnectedinaserialfashion.
Fig: LFSR

5. •TheXORofparticularoutputsarefedbacktothe
inputoftheLFSR.Ann-bitLFSRwillcyclethrough
2
n
–1statesbeforerepeatingthesequence.
•Theyaredescribedbyacharacteristicpolynomial
indicatingwhichbitsarefedback.

6. •Acompletefeedbackshiftregister(CFSR),shownin
Figure(b),includesthezerostatethatmaybe
requiredinsometestsituations.
•Ann-bitLFSRisconvertedtoann-bitCFSRby
addingann–1inputNORgateconnectedtoallbut
thelastbit.
Fig: CFSR

7. Signature Analyzer
•Asignatureanalyzerreceivessuccessiveoutputsof
acombinationallogicblockandproducesa
syndromethatisafunctionoftheseoutputs.
•Thesyndromeisresetto0,andthenXORedwith
theoutputoneachcycle.
•Thesyndromeisswizzledeachcyclesothatafault
inonebitisunlikelytocancelitselfout.
•Attheendofatestsequence,theLFSRcontainsthe
syndromethatisafunctionofallpreviousoutputs.

8. •Thiscanbecomparedwiththecorrectsyndrome
(derivedbyrunningatestprogramonthegood
logic)todeterminewhetherthecircuitisgoodor
bad.
•Thecombinationofsignatureanalysisandthescan
techniquecreatesastructureknownasBIST—for
Built-InSelf-TestorBILBO—forBuilt-InLogicBlock
Observation.

9. BIST/BILBO
Fig: Block diagram of BIST/BILBO

10. •The3-bitBISTregistershownintheaboveFig.isa
scannable,resettableregisterthatalsocanserveas
apatterngeneratorandsignatureanalyzer.

12. •C[1:0]specifiesthemodeofoperation.
•Intheresetmode(10),alltheflip-flopsare
synchronouslyinitializedto0.
•Innormalmode(11),theflip-flopsbehavenormally
withtheirDinputandQoutput.
•Inscanmode(00),theflip-flopsareconfiguredasa
3-bitshiftregisterbetweenSIandSO.
•Notethatthereisaninversionbetweeneachstage.
•Intestmode(01),theregisterbehavesasapseudo-
randomsequencegeneratororsignatureanalyzer.

13. •IfalltheDinputsareheldlow,theQoutputsloop
throughapseudo-randombitsequence,whichcan
serveastheinputtothecombinationallogic.
•IftheDinputsaretakenfromthecombinational
logicoutput,theyareswizzledwiththeexisting
statetoproducethesyndrome.
•BISTisperformedbyfirstresettingthesyndromein
theoutputregister.Thenbothregistersareplaced
inthetestmodetoproducethepseudo-random
inputsandcalculatethesyndrome.
•Finally,thesyndromeisshiftedoutthroughthe
scanchain.

14. Advantges
•Low cost
•Betterfaultcoverage
•Shortertesttime
•Allowtheconsumers themselves totest the chip
Disdvantges
•Additional Silicon area and fabrication process
required
•Onchiptesting hardware itself can fail