Introduction to CMOS VLSI Design for Low Power

Design for Low Power

1. Introduction to
CMOS VLSI
Design
Design for Low Power

2. CMOS VLSI DesignDesign for Low Power Slide 2
Outline
Power and Energy
Dynamic Power
Static Power
Low Power Design

3. CMOS VLSI DesignDesign for Low Power Slide 3
Power and Energy
Power is drawn from a voltage source attached to
the V
DDpin(s) of a chip.
Instantaneous Power:
Energy:
Average Power:( ) ( )
DD DD
P t i t V 00
( ) ( )
TT
DD DD
E P t dt i t V dt avg
0
1
()
T
DD DD
E
P i t V dt
TT


4. CMOS VLSI DesignDesign for Low Power Slide 4
Dynamic Power
Dynamic power is required to charge and discharge
load capacitances when transistors switch.
One cycle involves a rising and falling output.
On rising output, charge Q = CV
DDis required
On falling output, charge is dumped to GND
This repeats Tf
swtimes
over an interval of TC
f
sw
i
DD
(t)
VDD

5. CMOS VLSI DesignDesign for Low Power Slide 5
Dynamic Power Cont.C
f
sw
i
DD
(t)
VDD dynamic
P 

6. CMOS VLSI DesignDesign for Low Power Slide 6
Dynamic Power Cont.C
f
sw
i
DD
(t)
VDD  
dynamic
0
0
sw
2
sw
1
()
()
T
DD DD
T
DD
DD
DD
DD
DD
P i t V dt
T
V
i t dt
T
V
Tf CV
T
CV f







7. CMOS VLSI DesignDesign for Low Power Slide 7
Activity Factor
Suppose the system clock frequency = f
Let f
sw= af, where a= activity factor
–If the signal is a clock, a= 1
–If the signal switches once per cycle, a= ½
–Dynamic gates:
•Switch either 0 or 2 times per cycle, a= ½
–Static gates:
•Depends on design, but typically a= 0.1
Dynamic power:2
dynamic DD
P CV fa

8. CMOS VLSI DesignDesign for Low Power Slide 8
Short Circuit Current
When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
Leads to a blip of “short circuit” current.
< 10% of dynamic power if rise/fall times are
comparable for input and output

9. CMOS VLSI DesignDesign for Low Power Slide 9
Example
200 Mtransistor chip
–20M logic transistors
•Average width: 12 l
–180M memory transistors
•Average width: 4 l
–1.2 V 100 nm process
–C
g= 2 fF/mm

10. CMOS VLSI DesignDesign for Low Power Slide 10
Dynamic Example
Static CMOS logic gates: activity factor = 0.1
Memory arrays: activity factor = 0.05 (many banks!)
Estimate dynamic power consumption per MHz.
Neglect wire capacitance and short-circuit current.

11. CMOS VLSI DesignDesign for Low Power Slide 11
Dynamic Example
Static CMOS logic gates: activity factor = 0.1
Memory arrays: activity factor = 0.05 (many banks!)
Estimate dynamic power consumption per MHz.
Neglect wire capacitance.   
   

6
logic
6
mem
2
dynamic logic mem
20 10 12 0.05 / 2 / 24
180 10 4 0.05 / 2 / 72
0.1 0.05 1.2 8.6 mW/MHz
C m fF m nF
C m fF m nF
P C C f
l m l m
l m l m
  
  
  


12. CMOS VLSI DesignDesign for Low Power Slide 12
Static Power
Static power is consumed even when chip is
quiescent.
–Ratioed circuits burn power in fight between ON
transistors
–Leakage draws power from nominally OFF
devices0
1
gs t ds
TT
VV V
nv v
ds ds
I I e e
 

 
  0t t ds s sb s
V V V V       

13. CMOS VLSI DesignDesign for Low Power Slide 13
Ratio Example
The chip contains a 32 word x 48 bit ROM
–Uses pseudo-nMOS decoder and bitline pullups
–On average, one wordline and 24 bitlines are high
Find static power drawn by the ROM
–b= 75 mA/V
2
–V
tp= -0.4V

14. CMOS VLSI DesignDesign for Low Power Slide 14
Ratio Example
The chip contains a 32 word x 48 bit ROM
–Uses pseudo-nMOS decoder and bitline pullups
–On average, one wordline and 24 bitlines are high
Find static power drawn by the ROM
–b= 75 mA/V
2
–V
tp= -0.4V
Solution: 
2
pull-up
pull-up pull-up
static pull-up
24μA
2
29μW
(31 24) 1.6 mW
DD tp
DD
VV
I
P V I
PP
b



  

15. CMOS VLSI DesignDesign for Low Power Slide 15
Leakage Example
The process has two threshold voltages and two
oxide thicknesses.
Subthreshold leakage:
–20 nA/mm for low V
t
–0.02 nA/mm for high V
t
Gate leakage:
–3 nA/mm for thin oxide
–0.002 nA/mm for thick oxide
Memories use low-leakage transistors everywhere
Gates use low-leakage transistors on 80% of logic

16. CMOS VLSI DesignDesign for Low Power Slide 16
Leakage Example Cont.
Estimate static power:

17. CMOS VLSI DesignDesign for Low Power Slide 17
Leakage Example Cont.
Estimate static power:
–High leakage:
–Low leakage:  
66
20 10 0.2 12 0.05 / 2.4 10mml m l m     
  
6
66
20 10 0.8 12 0.05 /
180 10 4 0.05 / 45.6 10
m
mm
l m l
l m l m

      
   
6
6
2.4 10 20 / / 2 3 /
45.6 10 0.02 / / 2 0.002 /
32
38
static
static static DD
I m nA m nA m
m nA m nA m
mA
P I V mW
m m m
m m m
    

 




18. CMOS VLSI DesignDesign for Low Power Slide 18
Leakage Example Cont.
Estimate static power:
–High leakage:
–Low leakage:
If no low leakage devices, P
static= 749 mW (!)  
66
20 10 0.2 12 0.05 / 2.4 10mml m l m     
  
6
66
20 10 0.8 12 0.05 /
180 10 4 0.05 / 45.6 10
m
mm
l m l
l m l m

      
   
6
6
2.4 10 20 / / 2 3 /
45.6 10 0.02 / / 2 0.002 /
32
38
static
static static DD
I m nA m nA m
m nA m nA m
mA
P I V mW
m m m
m m m
    

 




19. CMOS VLSI DesignDesign for Low Power Slide 19
Low Power Design
Reduce dynamic power
–a:
–C:
–V
DD:
–f:
Reduce static power

20. CMOS VLSI DesignDesign for Low Power Slide 20
Low Power Design
Reduce dynamic power
–a: clock gating, sleep mode
–C:
–V
DD:
–f:
Reduce static power

21. CMOS VLSI DesignDesign for Low Power Slide 21
Low Power Design
Reduce dynamic power
–a: clock gating, sleep mode
–C: small transistors (esp. on clock), short wires
–V
DD:
–f:
Reduce static power

22. CMOS VLSI DesignDesign for Low Power Slide 22
Low Power Design
Reduce dynamic power
–a: clock gating, sleep mode
–C: small transistors (esp. on clock), short wires
–V
DD: lowest suitable voltage
–f:
Reduce static power

23. CMOS VLSI DesignDesign for Low Power Slide 23
Low Power Design
Reduce dynamic power
–a: clock gating, sleep mode
–C: small transistors (esp. on clock), short wires
–V
DD: lowest suitable voltage
–f: lowest suitable frequency
Reduce static power

24. CMOS VLSI DesignDesign for Low Power Slide 24
Low Power Design
Reduce dynamic power
–a: clock gating, sleep mode
–C: small transistors (esp. on clock), short wires
–V
DD: lowest suitable voltage
–f: lowest suitable frequency
Reduce static power
–Selectively use ratioed circuits
–Selectively use low V
tdevices
–Leakage reduction:
stacked devices, body bias, low temperature