Introduction to Design for Test "DFT".pdf

Design for Test (DFT) is an approach for making manufactured products, especially complex integrated circuits, easier and more cost-effective to test by integrating testability features directly into the initial design phase. This method enhances test coverage, improves manufacturing yield, reduces testing time and costs, and ultimately leads to higher quality products by allowing for efficient identification and diagnosis of manufacturing defects or functional anomalies.

1. Ahmed AbdelazeemAhmed Abdelazeem
Introduction to Design for
Test
Ahmed Abdelazeem

2. Ahmed Abdelazeem
üNeed for test for VLSI designs after fabrication
üDefects in VLSI fabrication
üDifferent test methods in ASIC designs
üDifferent test methods in ASIC designs
üClassification of testing
01Introduction to Design for Test

3. Ahmed Abdelazeem
What is Manufacturing Test?
•High-volume production testing is a pass/fail proposition.
•Only good ICs are shipped to customer
•Manufacturing process causes defects
•Before ICs are shipped, they are tested to check if they are
good
•Failed ICs are rejected
•Testing is a decision
•ATE supplies test stimulus to the IC die or packaged IC
and captured its response to compare with expected
results
Manufacturing
Process
IC Testing
Shipped to customers
Pass
Fail
Rejected

4. Ahmed Abdelazeem
Testing of Electronic Systems
•The rule of Ten: The cost of discovering a defective chip increases by an order of magnitude at each
successive level of integration, from die/package, board and system.
•The economical model of cost/profit for an IC-based system must also include testing to place in the
balance:-Cost of testing and testing equipment, testing time overhead-Cost of shipping defective ICs, or systems that need further repair
Test and
repair costComponent
Board
System
Field
1
10
100
1000
Product Phase

5. Ahmed Abdelazeem
Test Cost/Quality Trade-off
Cost of quality
Cost of
the fault
Cost of
testing
Quality
Cost
100%0%Optimum
test / quality
Generally, in the IC
industry, the actual goal or
requirement is to have no
defect in a released chip.
This means nearly 100%
test coverage is required.
The capability and cost of
such testing needs to be
managed by DFT.

6. Ahmed Abdelazeem
Manufacturing Defects in IC Fabrication (1/5)
•What are the manufacturing defects in IC
fabrication?
•They manifest as defects at electrical level as:
qShort circuit faults
vShorts occurring between metal and VDD or
GND
vGate oxide faults to drain or source of
transistor
vThey can become pattern dependent faults
qBridging faults
vShorts between two metal interconnects as
bridge
qDelay faults
•They are modeled as faults at logic and
behavioral levels
Hillocks in wires due to stress Electromigration
Antenna effect
During fabrication process
After fabrication process
Dishing and Erosion
Erosion 1Erosion 2Dishing

7. Ahmed Abdelazeem
•Physical defects are due to failure mechanisms in the
fabrication processes.
•Some of them are:
qExtra and missing materials:
oCan be caused bydust particleson the mask,
wafer surface or processing chemicals, such
as, photoresist.
oDuring photolithography, these particles lead
tounexposedphotoresist areas, leading to:
-Unwanted materialorunwanted
etchingof the material.
-Causesshortsandopensin the poly,
active, or metal layers.
Physical defectPhysical model
Logic faultsLogic faults
Manufacturing Defects in IC Fabrication (2/5)

8. Ahmed Abdelazeem
qGate Oxide Shorts (GOS)
vPinhole defects are common thin-ox defects, which are caused by:
-Insufficient oxygen at the interface of Si and SiO2
-Chemical contamination
-Nitride cracking during field oxidation
-Crystal defects
-Imperfections in a uniform growth pattern of the thin oxide layer
-Particulate contamination in the thin oxide mask
qAGOScan also be created in post fabrication procedures andoperational conditions:
vElectric field stress due to scaled down feature size without scaling supply voltage.
vElectrostatic discharge (ESD).
vTrapping of charge introduced by hot electrons.
vMight develop later due to an effect called time dependent dielectric breakdown (TDDB).
vCan exhibit pattern dependent faults.
Manufacturing Defects in IC Fabrication (3/5)

9. Ahmed Abdelazeem
qElectromigration
vOne of the major failure mechanisms in
interconnects.
vAluminum has a low melting point, and
high current densities can displace metal
atoms.
-Scaling is reducing themean time to
failure(MTTR), which is:
vProportional to the width and thickness of
the metal lines.
vInversely proportional to the current
density.
vComplete defect characterization is
difficult.
vNew failure mechanisms or old ones that
become more prevalent through scaling
make this a challenging problem.
Top View
Cross section View
Metal 1
Metal 1
Splinter 1
Splinter 2
Void
Metal 2
Metal 1
Manufacturing Defects in IC Fabrication (4/5)

10. Ahmed Abdelazeem
lWire bonding failures
nBridges are undesired electrical connections between two
or more wires in an IC, resulting from extra conducting
material or missing insulating material.
nOpens are difficult to detect.
They are due to process variations such as
§Random fluctuation in process environment
§Turbulent flow of gases used for diffusion and oxidation
§Inaccuracies in the control of furnaces
§Variations in chemical and physical properties of
materials such as
vFluctuation in the density and viscosity of
photoresist
vWater and gas contaminations
§ICs fail at different stages of life cycle shown as bathtub
curve
IC life cycle
Bathtub curve
Escaped
Defects
Wear Out
Defects
Random
Defects
Manufacturing Defects in IC Fabrication (5/5)

11. Ahmed Abdelazeem
Need for Testing of VLSI Designs After Fabrication
•Test decisions§True Pass§True Fail§False Positive: Defective ICs passing tests cause Test
escape. This is referred as under testing.§False failure: Yield loss is declaring working ICs as
failed. This is referred as over killor over testing.•Goal of good testing is to minimize Test escapesand Yield
Loss§This is a tradeoff between test quality and test cost§Test Quality reduces Test escape but increases yield loss§Low-cost test reduces yield loss but increases test escapes
Good ICDefective IC
Pass
Tests
True PassTest escape
Fail
Tests
Yield LossTrue Fail

12. Ahmed Abdelazeem
Importance of Testing
•Testing guarantees quality of ICs§By reducing test escapes§Confirms functionality and reliability of ICs•Reduces time to market§By enabling prototype testing and debug§Improves efficiency of production testing§Improves yield by enabling diagnosis of failed ICs•Enhances ROI§Reduces test cost§Support fixing failing ICs in some cases§Improves yield•Figure shows the IC product flow
IC production flow

13. Ahmed Abdelazeem
Need for Test of VLSI Designs After Fabrication
•Before ICs are shipped, they are tested to check if they
are good•IC testing is done using automated test equipment
(ATE)•Typically, ICs are tested in two stages§Wafer level using probe cards with ATEs§Packaged level also called final testing•ATE supplies test stimulus to the IC die or packaged IC
and captures its response to compare with expected
results •The test head with probe pins can step and repeat from
die to die providing access to pads of different dies one
by one
Do you know how
ICs are tested at
wafer level and
package level?
Video Source: Teradyne.com

14. Ahmed Abdelazeem
Wafer Testing
•Testing at wafer level uses probing stations on ATE•Prober enables access to I/O pads of the die and interfaces with the ATE•The test head can step and repeat from die to die providing access to pads of different dies one by one•ATE is used both at the wafer level and final stage•Wafer is secured on the prober with the vacuum suction for stability•Probe card is interfaced with ATE electronics which issues stimulus and collects response from the dies
and compares with the expected response
Wafer Prober
How does
wafer prober
operate?

15. Ahmed Abdelazeem
Final Testing
•Testing at package level uses ATE•Probers of wafer level are replaced by IC socket holders called load boards•The output of ATE testing helps you classify ICs as good or bad
ATE Testing of ICs
How are ICs
Tested using
ATEs?

16. Ahmed Abdelazeem
Responsibility of Developing Good IC Testing
•Design for testability
•Built-in self test
Design team
•ATE testing and maintenance
•Test data analysis
Test service
•Yield improvement
•Defect diagnosis
Fabrication
•Test cost reduction
•Test quality assurance
Test team
•Automatic test vector generation
•Fault simulations
EDA
•Diagnosis
Physical failure analysis

17. Ahmed Abdelazeem
Different TestMethods of ICs
Functional testing
Structural testing
Scan based delay testing
Built-in self testing
Memory testing
Analog circuit testing
Reliability testing
Functional IC testers
In-circuit structural
IC testers: scan,
BIST, memory
Reliability
IC testers

18. Ahmed Abdelazeem
Manufacturing Test
•A speck of dust on a wafer is sufficient to harm chip•Yield of any waferis < 100%
qMust test chips after manufacturing before delivery to customers to only ship good parts•Manufacturing testers are •very expensive
qMinimization of time on tester
qCareful selection of test vectors
http://www.yokogawa.com/pr/Corporate/News/2010/img/20101118-l.jpg

19. Ahmed Abdelazeem
http://www.spherea.com/sites/default/files/upload/illustration_sesar_3000.jpg
ATE Example: SESAR 3000 GPATE

20. Ahmed Abdelazeem
ATE Example: Agilent 93000
•Workstation
-Test software, interface and control of mainframe
-Test engineer computer
•Mainframe
-Test computer
-Power sources
-Measurement instruments
•Testhead
-Device Interface Board (DIB) to Device Under Test (DUT)
-Sensible measurement equipment kept close to DUT
http://www.jmcserv.com/Photo_Configs/Spares/93k_E7018%20AB%2001.jpg

21. Ahmed Abdelazeem
Probers
Electroglas, Inc.
http://content.edgar-online.com/edgar_conv_img/2004/03/24/0001193125-
04-048241_G47346G32J18.JPG
•Robotic machine that manipulates the wafers
•Connects individual chip to probe card needles
•ATE is connected for measurement
•ATE wafer probes can only connect to pre-existing chip
IO pads or dedicated test pads
Wentworth Laboratories
Cantilever Probecard
http://www.winwayglobal.com/wli/verimax/imag
001.jpg
MProbe Card
http://amst.tradekorea.com/product/det
ail/P297458/MProbe-Card.html
Probe Card Pins (Needle Tips) Contacting the Wafer
https://www.toyo-denshi.co.jp/en/service/wafer/whats.html

22. Ahmed Abdelazeem
Roles of Testing
•Detection:determination whether or not the device under test (DUT) has any faults§Identification of process flow§Detection of chips that must not be sold to customers•Diagnosis:location and identification of a specific fault that is present on DUT•Device characterization: identification of errors in the actual design or in the testing procedure•Failure mode analysis (FMA):determination of manufacturing process errors that may have
caused defects on the DUT§Used in all stages of test to improve the manufacturing process and the number of fault-free chips

23. Ahmed Abdelazeem
•ASICs pose different challenges at different stages of design and development
•The ASIC design and development flow is very complex
•The cost of design and fabrication of ASICs is very high
•Design and fabrication of ASICs is very sophisticated and require a high level of precision and
accuracy
To ensure ASICs work as intended, different test techniques are to be adopted at
different stagesof design and development. Different test parameters are important
at different stages.
Need for Variety of ASIC Testing Methods

24. Ahmed Abdelazeem
ASIC
Testing
ASIC design
verification
Test
verification
Characteriza
tion test
Production
test
Wafer test
Go-NoGo
test
DC
parametric test
AC
parametric test
Logic testDelay testFunctional
testIDDQ test
Package testSystem test
Reliability
test
Burn in Life test
Diagnosis
test
Different Types of ASIC Testing

25. Ahmed Abdelazeem
Fault Models
•Physical
-Short connection, open circuit, defect
•Logic
-Stuck at 1 and Stuck at 0, bridging
•Fault affect
-Fatal
-Parameters’ degradation

26. Ahmed Abdelazeem
•Physical short is a Defect
•Defectresulting in stuck-at behavior can be modeled as a stuck-at 1/0 Fault
•Malfunction of the system due to this Faultis a Failure
>=1
&
&
Stuck at 0 Fault
DefectFaultFailure
Example of Defect-Fault-Failure

27. Ahmed Abdelazeem
•DFT is adding extra logic to the chip
-Enabling physical testing of each unit separately
•DFT uses a set of tests that uncover
-Manufacturing defects
Test performed in Production
-Wear-out defects
Test performed during Production/In-field
•DFT affects all design aspects
-Area
-Routing
-Power
-Timing
Design For Test

28. Ahmed Abdelazeem
Fault
Universe
Systematic
Faults
(SW /HW)
Design
Bugs
Random
Faults
(HW)
Permanent
Manufacturing
SoC Aging
(In-field)
Transient
Alpha
Particles
•Documentation
•Verification
•SCAN
•Memory BIST
•Logic BIST
•Memory BIST
•ECC
•DCLS
•TMR
ECC: Error Correction Code
DCLS: Dual Core Lockstep
TMR: Triple Modular Redundant
SoC Fault Universe

29. Ahmed Abdelazeem
•Wafer sort is done on each die of the wafer
•A small probe card with thin flexible pins
-Touching each pad of the die
•Wafer sort test program might include:
-SCAN
-Memory BIST
-Boundary scan
-Analog test
-Basic functional test
Wafer Sort

30. Ahmed Abdelazeem
•Sawing machine cuts the dies
•Good dies are sent to the assembly house
Cutting the Wafer

31. Ahmed Abdelazeem
•Final test is run on each packaged chip
•The added value of final test
-Use board with peripherals
-Stress test: Extreme voltage/temperature conditions
-Detect packaging defects
Final Test

32. Ahmed Abdelazeem
Motivation
PowerPerformance
•Maximize processing
performance (utilization)
•Optimize power efficiency
•Extend reliability
Context
•Major processing tasks
•Large die
•High power
•Low VDD
•2.5D, 3D packaging
•Interconnect resistance
•FinFET technology
Challenges
•Multiple hotspots
•Voltage droops
•Process variation FF…SS
•Difficult to predict workloads
•Too much power or not enough
Challenges of FinFETSoCs

33. Ahmed Abdelazeem
AI
•Major thermal challenges due to massive compute workloads
•High power distribution and IR drops
•High power limits performance, increases OpEx $ & CO2 emissions
Data Center
•Reduce power to save OpEx $ & CO2 emission footprint
•Maximize performance
•High reliability
Automotive
•Long operational lifecycle (15+ years)
•Demanding QA and functional safety requirements
•Compute requirements increasing dramatically
•Low latency decision making and low power
Consumer
•Thermal challenges & user experience with data intensive workloads
•Battery life
•High data throughput/ low latency
Challenges by Application

34. Ahmed Abdelazeem
Embedded Process, Voltage, and Temperature (PVT) monitoring is
critical to achieve successful operation and compelling performance
of advanced node and FinFET semiconductor devices.
Features:
•Full suite of embedded monitoring IP managed by a PVT
controller
•Local sensing for multi-processor architectures
•Flexible, modular configuration, with standard interfaces
Benefits:
•Maximizes performance, power, reliability
•Highly accurate, distributed sensing throughout the die
•Multi-site, in-core monitoring for HPC
Associated Silicon Lifecycle Management (SLM) Phases
Environmental Monitors

35. Ahmed Abdelazeem
•According to test objective
-Production test also called Go-NoGo tests for volume testing
-Characterization test carried out to characterize the device. Device data sheets contain the results of these tests
-Reliability tests to detect reliability defects over time
-Diagnosis tests to debug the faulty ICs to locate the defect location
•According to development stage
-Wafer testing (wafer sort) to separate good dies from bad dies. Only good ones are sent for packaging
-Package test or final test to separate good ICs vs bad ones. Only good ones are supplied to customers
-System tests used to test the chip in complete integrated system
•According to test parameters
-DC test
-AC test
-IDDQ test
-Delay test
-Functional test
-Logic test
Test Classification

36. Ahmed Abdelazeem
Wafer sort
ATE with prober
Laser repair
Manual
Packaging
Wire bonding and package seal
Final test
ATE with IC loader
Subject to environmental chambers
Post burn-in test
ATE Go-NoGO
Final test
Go-NoGo test
MarkingVisual inspectionShip to Customers
Depending on the test cost and quality production, the flow is customized
Production test floor
Load boards and test fixture
to interface load board and ATE
Flow diagram
Production Test Flow

37. Ahmed Abdelazeem
•Done using ATE with the wafer prober assembly
•Probe card contains number of probe pins
thatare connected to the backend connector
through which the cable is connected to ATE
•ATE can be common for wafer and final tests
•Wafer to be tested is mounted on the probe
station using vacuum loading for test
•Probe pins connect die pads on wafer to the
connector and a cable system and to the ATE
electronics
•Probe card assembly is done carefully balancing
inductance and capacitance of each pin
-Wafer map shows the test results with pass/fail bins
-Each die is marked with marking ink of different colors
Wafer tester with probe card
Source: Teradyne
ATE
Probe card assembly
Wafer map
Wafer Testing

38. Ahmed Abdelazeem
•Sample dies are tested thoroughly
•Goal is to confirm IC functions as intended
•Confirm required specifications are met
•Tested at all rated conditions including process corners
•This helps to develop production test as part of this test is considered for Go-NoGo tests
•Results are mapped as Shmoo plots as shown in the figure. A Shmoo plot is a graphical display of the
response of a device or system varying over a range of conditions or inputs.
fail
Pass
Device Characterization

39. Ahmed Abdelazeem
•Built-in self-tests of logic during initialization
•ECC test whenever the data is read from the memory
•CRC checks for data integrity
•These are done when the device is in operation
•Watchdog timer test when critical events occur in system level test
•Needed for mission critical SoC applications
Implicit Testing

40. Ahmed Abdelazeem
References
•L. Tripathi, S. Saxena, S. Kumar Mohapatra. Advanced VLSI Design and Testability Issues. CRC
Press; 1st Edition. 2020•Robert Benefield; Lean DevOps: A Practical Guide to On Demand Service Delivery 1st Edition;
2022•Gerardus Blokdyk; Very Large-Scale Integration VLSI Second Edition; 2022•Anand D. Darji, Deepak Joshi; Advances in VLSI and Embedded Systems: Select Proceedings of
AVES 2021 (Lecture Notes in Electrical Engineering, 962); 2022 •David M. Anderson; Design for Manufacturability: How to Use Concurrent Engineering to
Rapidly Develop Low-Cost, High-Quality Products for Lean Production, Second Edition; 2022

41. Ahmed Abdelazeem
Chapter Summary
Introduction to Design for Test

42. Ahmed AbdelazeemAhmed Abdelazeem
Thank You J