Introduction to sequential circuit and logic circuits

Introduction to sequential circuit

1. Introduction to Sequential Circuits

2. Logic Circuits
•Combinational Logic:
–Output depends only on current input
–Has no memory
•Sequential Logic:
–Output depends not only on current input but also on past
input values, e.g., design a counter
–Need some type of memory to remember the past input
values

3. Sequential Logic Circuits
•remember past inputs and past circuit state
•Outputs from the system “fed back” as new inputs
•The storage elements are circuits capable of storing binary
information: memory
•result of one step as an input to the next

4. Sequential Circuits

5. Definitions
•Inputs –All the outside logic signal inputs to the circuit.
Typically, the clock is not consider part of the signal inputs of
the circuit.
•Outputs –The logic signal outputs.
•Present State –the logic value of all the state variables of the
system. These are stored in the state memory.
•Next State –Given the present state and the current values on
the inputs, the next state represents the next logic state the
circuit will transition to on the next clock.

6. Analysis of Sequential Circuits
Input: x(t)
Output:y(t)
State:A(t), B(t)
states of flipflops A, B
t –clock signal
Inputs at every edge
Output changes accordingly
with respect to the changes
in the states of the flipflops
Transition Q(t) –Q(t+1)
on clock edge
State changes A(t+1)
B(t+1)

7. State Changes in Flipflops
State changes follow the positive edge of clock pulses and the DATA input
Q(t) Q(t+1)
Q(t) Q(t+1)

8. State of the Circuit
•Boolean equations
B(t+1) = A’(t)x(t)
A(t+1) = A(t)x(t) + B(t)x(t)
= x(t) (A(t)+B(t))
y(t) = x’(t)(B(t) + A(t))
C
DQ
Q
C
DQ
Q'
y
x
A
A’
B
CP
Next State
Output

9. State Table
Present StateInputNext StateOutput
A(t) B(t) x(t)A(t+1) B(t+1)y(t)
0 0 0 0 00
0 0 1 0 10
0 1 0 0 01
0 1 1 1 10
1 0 0 0 01
1 0 1 1 00
1 1 0 0 01
1 1 1 1 00

10. State Table Characteristics
A multiple variable table with four sections
Present State–values of state variables for each state
Input–input combinations
Next state–value of the state at (t+1)
based on present stateand input
Output–value of the output
function of present state
and (sometimes) input.

11. State Diagram
A B
0 0
0 1 1 1
1 0
x=0/y=1
x=1/y=0
x=1/y=0
x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
x=0/y=0
x(t)010110011101010
y(t)001001000010101

12. (1) For the given input-output sequence,
(a) How many clock cycles will be needed?
(b) How many times the machine goes to the state 00, 01, 10 and 11?
(c) Plot the output sequence with reference to the clock signal.
Refer next slide
(2) What will be the output sequence for the following input sequence?
(3) What will be the output if the circuit receives input 0 immediately after
starting from the state 11? Will it be the correct circuit behaviour? Why?
x(t)010110011101010
y(t)001001000010101
x(t)101011000111001
y(t)=?

13. CLK
x(t)
y(t)

14. Present
State
A(t) B(t)
Next State Output
A(t+1) B(t+1)A(t+1) B(t+1)y
x=0 x=1x=0x=1
0 00 00 10 0
0 10 01 11 0
1 00 01 01 0
1 10 01 01 0
Equivalent State Diagram
Present StateInputNext StateOutput
A(t) B(t) x(t)A(t+1) B(t+1)y(t)
0 0 0 0 00
0 0 1 0 10
0 1 0 0 01
0 1 1 1 10
1 0 0 0 01
1 0 1 1 00
1 1 0 0 01
1 1 1 1 00

15. State Diagram
A
C
D
x=0/y=1
x=1/y=0
x=1/y=0
x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
x=0/y=0
B
A B
0 0
0 1 1 1
1 0
x=0/y=1
x=1/y=0
x=1/y=0
x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
x=0/y=0

16. State Diagrams
A graphical form with the following components:
Circle–state name in it for each state
Directed Arc–Present State to Next State
for each state transition
Label–on each directed arc with Input value
which causes the state transition
•On each circle with the output value produced, or
•On each directed arc with the output value produced.

17. State Redundancy
A
B
x=1/y=0
x=0/y=1
x=0/y=0
x=1/y=0
A
C
D
x=0/y=1
x=1/y=0
x=1/y=0
x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
x=0/y=0
B
Present
State
Next StateOutput y
x=0x=1x=0x=1
A A B 0 0
B A B 1 0
Present
State
Next StateOutput y
x=0 x=1x=0x=1
A A B 0 0
B A C 1 0
C A D 1 0
D A D 1 0

18. State Redundancy
x(t)010110011101010
NS ABABCAABCDABABA
y(t)001001000010101
A
C
D
x=0/y=1
x=1/y=0
x=1/y=0
x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
x=0/y=0
B

19. A
0
x=1/y=0
x=0/y=1
x=0/y=0
x=1/y=0
x(t)010110011101010
NS ABABBAABBBABABA
y(t)001001000010101
State Redundancy

20. Design of Sequential Circuits
FSM
finite state machines
functional behavior of these circuits represented using a finite no. of states

21. Types of Machines
Moore Machine
Mealy Machine

22. Mealy Machine
9/26/2008 22ECE 561 -Lecture 4Next
State
Logic
Output
Logic
State
Memory
(F/F)
CLOCK
Inputs Excitation
Current
State
Outputs
Characterized by –Outputs are a function of both inputs and current state

23. Moore machine
Characterized by –Outputs are a function current state onlyNext
State
Logic
Output
Logic
State
Memory
(F/F)
CLOCK
Inputs Excitation
Current
State
Outputs

24. Design Problem
Specifications
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of a clock signal.
3. The output z is equal to 1 if during two immediately preceding clock cycles
the input was equal to 1. Otherwise, the value of z is equal to 0.
z cannot depend solely on the present value of w.
different states in the circuit that determine the value of z.
sequence of values of the w and z signals during 11 clock cycles

25. State Diagram

26. State Table