Introduction to Submicron CMOS Technology and Device Modeling

About VLSI

1. AY-2025-2026 ODD SEM Department of ECE Session - 2 Mixed Signal IC design 22vls3505 Topic: Submicron CMOS:CMOS Process Flow

2. AIM OF THE SESSION To provide an in-depth understanding of submicron CMOS technology, including device modeling, process flow, and its application in digital and analog circuit design. To enable students to apply CMOS principles in designing and analyzing both digital logic blocks and analog building blocks using modern submicron processes. INSTRUCTIONAL OBJECTIVES This Session is designed to: Explain the CMOS process flow and identify key fabrication steps including capacitor and resistor formation. Describe how MOSFETs function as switches in digital circuits and analyze delay elements and adder circuits. Illustrate analog design principles such as biasing, operational amplifier configuration, and key noise sources. Relate the role of compact models and short-channel effects to performance in submicron CMOS technologies. LEARNING OUTCOMES At the end of this session , you should be able to: Analyze and design basic digital and analog circuits using submicron CMOS models. Interpret CMOS process flow diagrams and recognize how passive elements like capacitors and resistors are integrated on-chip. Evaluate the impact of process and device-level parameters on the performance and noise behavior of analog and digital circuits.

3. 3 CMOS = Complementary Metal Oxide Semiconductor Submicron refers to feature sizes < 1 µm Process flow involves multiple steps to create NMOS and PMOS on a single wafer. Importance: Determines performance, yield, cost. Introduction to CMOS Process Fig: Schematic view of the CMOS process flow.

4. 4 Starting Material – Silicon Wafer Fig: Silicon Wafer Process High-purity single-crystal silicon Types: p-type (doped with Boron) n-type (doped with Phosphorus) Typical diameter: 200mm, 300mm

5. 5 Oxidation Fig: Semiconductor Wafer Thermal Oxidation Method Thermal oxidation forms SiO ₂ layer on Si Acts as gate oxide or isolation Dry oxidation (thin, high quality) Wet oxidation (thicker, faster growth)

6. Photolithography Patterning technique using light and masks Coating Aligning Exposing Developing photoresist Positive vs Negative resists Resolution limited by wavelength Deep UV EUV Fig: Photolithography process steps: coating of photoresist on the substrate, mask placed over upper layer and exposed to UV radiation, resist development and stripping ion etching process, final QD structure after process.

7. Etching Removes layers not protected by photoresist Types: Wet (chemical) Dry (plasma, RIE) Submicron tech uses anisotropic dry etching for vertical profiles Selectivity: Etch one layer without damaging other Fig: Anisotropic and isotropic plasma etching

8. Doping – Ion Implantation Introduce carriers (electrons/holes) by implanting dopant ions NMOS: Phosphorus/Arsenic PMOS: Boron Precise control of dose, depth, and location Followed by annealing to activate and repair crystal damage Fig: basic structure of an ion implanter with magnetic analysis .

9. Gate Formation Gate oxide: ultra-thin SiO ₂ (~1-2 nm in submicron) Gate electrode: polysilicon (older) or metal (modern) Defines channel length (L) → critical in submicron scaling Modern nodes use High-k / Metal Gate (HKMG) for leakage control Fig: MOSFET Structure

10. Spacer Formation and S/D Engineering Spacer: Deposited sidewall layer (usually Si₃N ₄) Forms after gate etch to protect gate side LDD (Lightly Doped Drain) near channel HDD (Heavily Doped Drain) after spacers Reduces hot-carrier and SCE effects Fig: submicron MOSFET with sidewall spacers :

11. Passivation, Dicing & Testing Final passivation layer: protects IC from environment Wafer : diced into individual dies Electrical testing: functional, parametric Good dies are packaged into ICs (e.g., QFN, BGA, DIP) Fig: Wire Bonding Process in Semiconductor industry

12. Conclusion and Future Trends Submicron CMOS drives modern electronics Key is balancing performance, power, and area (PPA) Future: CFET (Complementary FET) 3D stacked transistors AI-assisted chip design Need for improved models and tools Fig: Evolution of Transistors

13. THANK YOU Team – LOW POWER VLSI Design 13 Prepared by Dr. K.Girija Sravani