Introduction to VLSI – Very Large scale integration.pptx

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1. Introduction to VLSI – Very Large scale integration Digital IC’s are classified according to the number of transistors and logic gates fabricated on single chip. This classification system helps categorize Ics based on their complexity and functionality Small Scale Integration (SSI): SSI IC’s contain a small number of logic gates or equivalent components, typically up to 10 gates per chips. These ICs are used for simple digital functions. Medium Scale Integration (MSI): MSI IC’s integrate a moderate number of logic gates, typically up to hundreds of gates per chip. They are capable of implementing more complex digital functions than SSI IC’s such as binary adder, subtractors , decoder, encoder, and multiplexer. Large scale Integration(LSI): LSI Ics integrate many logic gates, typically thousands to tens of thousands of gates per chip. They are capable of implementing even more complex digital functions and are commonly used in microprocessor and memory chips Very Large Scale Integration(VLSI): VLSI Ics integrate a huge number of logic gates, typically hundreds of thousands to millions of gates per chip. They are used in highly complex digital systems, such as advanced microprocessor, Application-Specific Integrated Circuits(ASICs) and System-on-Chip ( SoC ) designs.

2. Ultra Large Scale Integration (ULSI): It represents the most advanced level integration in digital integrated circuits. ULSI ICs incorporate millions to billions of transistors or gates on a single chip. Classification Number of Logic gates Examples Small-Scale Integration(SSI) Up to 10 Basic logic gates (AND, OR, NOT) Medium Scale Integration (MSI): 10-99 Counters, Multiplexers, Decoders, Encoders Large scale Integration(LSI): 100-999 Memory Chips, Programmable Logic Devices Very Large Scale Integration(VLSI): Above 1000 Microprocessors, microcontrollers. ASICs, SoCs Ultra Large Scale Integration (ULSI): Millions to billions of gates Highly advanced microprocessor, memory devices and System-on-Chip( SoC ) design

3. Channel Length Definition: The Channel length in a MOSFET refers to the distance between the source and the drain regions. It’s a crucial parameter in the design and operation of MOSFETs because it significantly affects the device’s electrical characteristics. The channel length is typically denoted as L. Effects of shorter channel length Shorter channel lengths generally lead too higher drive currents and faster switching speeds. Shorter channel lengths introduce the challenges such as increased leakage currents and more pronounced short channel effects such as reduction in threshold voltage and carrier velocity saturation. A shorter channel length also results in a higher trans conductance, allowing for stronger control of the current flow with the gate voltage. Shorter channel lengths introduce hot carrier effects because they create very strong electric fields within the device.

4. Methods of VLSI CMOS Manufacturing 1) n-well process : In this method, a layer of n type (negative) dopant is diffused into a p-type (positive) substrate, creating a isolated n-type region called n well within the p-type substrate. This n-type region serves as the well for fabricating the p-channel MOS TRANSISTOR. n-well p-substrate P+ P+ n+ n+ n+ P+ P+ n+ B S D S D B G G NMOS PMOS CMOS transistor with n-well

5. P-well Twin well process Silicon On Insulator(SOI)

6. N-well Method of VLSI CMOS manufacturing Step 1 : Substrate selection : First we choose a substrate as a base for fabrication. For n-well, a p-type silicon substrate is selected. Step 2 : Creation of n-well in p-type substrate : This process involves following sub steps. Oxidation : I thin layer of insulating silicon dioxide is deposited on the substrate by exposing the substrate to high quality Oxygen and hydrogen in an oxidation chamber at approximately 10000 degree Celsius Growing of photoresist : At this stage a high sensitive material called photo resist is applied on to the substrate’s surface using spin coating. Masking : In this step, a desired pattern of the mask is applied over the photoresist and the substrate is then exposed to UV rays. The photoresists becomes either soluble or insoluble upon exposure to light, depending on positive photoresists or negative photoresists, respectively.

7. P-type substrate P-type substrate SiO2 P-type substrate SiO2 Photoresists P-type substrate SiO2 Photoresists P-type substrate SiO2 Photoresists P-type substrate SiO2 Photoresists P-type substrate SiO2 P-type substrate SiO2 N-well P-type substrate N-well Oxidation Growing Photoresists Masking with + ve photoresists Removal of exposed photoresists Etching Removal of photoresists layer Creation of n-well Removal of oxidation layer

8. Removal of exposed photoresist: The positive photoresist at the exposed region is removed by dissolving it using a chemical such as trichoroethylene . Itching: The abstract is immersed in an itching solution of hydrofluoric acid to remove the oxide layer and create opening in the oxide layer corresponding to the n-well pattern. Removal of whole photoresists layer: The entire photoresist mask is now stripped off with a chemical solvent (hot H2SO4) Formation of n-well: The n type impurities are diffused into the P type substrate through the exposed region thus forming n-well Removal of SiO2: The layer of sio2 is then removed by using hydrochloric acid.

9. Step 3: Gate Stack Formation; A thin layer of gate dielectric (usually silicon) and then a layer of polysilicon(conductive silicon) is deposited on the entire substrate. Photolithography is used to define the gate electrode patterns for individual transistors. Etching removes unwanted polysilicon, leaving behind patterned gate electrodes on the gate dielectric. n-well p-substrate

10. Step 4: Diffusion of three n+ regions: Oxidation process : An oxidation layer is deposited over the wafer which acts as a shield for further and metallization processes. Masking and diffusion : For making regions for diffusion of n-type impurities using masking process small gaps are made. Diffusion process : Three n+ regions are developed for the formation of terminals of NMOS. Removal of oxide : The oxide layer is stripped off. Step 5: Diffusion of three p+ regions: Similar to the n-type diffusion for forming the terminals of PMOS p-type diffusion are carried out.

11. Step 6 – Forming the metal terminals Contact etching : Before metal deposition, small openings, called vias , are etched through the insulating layers (oxide and nitride) on the wafer. These vias expose the underlying source, drain and gate regions of the transistors, enabling electrical contact with the metal interconnects. Photolithography is typically used to define the via pattern. Metal deposition : A thin layer of metal, typically aluminum is deposited across the entire wafer surface techniques like sputtering or evaporation. The thickness of the metal layer is precisely controlled to ensure proper conductivity and avoid excessive resistance. Patterning and etching : The photomask is used to expose the desired metal interconnection pattern and develop the photoresist, revealing the pattern. The etching process then removes unwanted metal portions, leaving behind the designed network of metal interconnects. Photoresists removal : The remaining photoresist is striped off the wafer surface, revealing the final interconnect network.

12. Step 7: Assigning the terminal names: Names are assigned to the terminals of NMOS and PMOS transistors.