Inverters_VLSI_Design powerpoint presentation

Inverters in VLSI for Electronics and Communication Engineering.

1. 5 March 2024 VLSI Design 15 March 2024 15 March 2024 1
VLSI Design
Dr. T R Lenka
Asst. Professor
Deptt of Electronics & Comm Engg.
National Institute of Technology Silchar
E-mail: [email protected]
MOS Inverters

2. Assignment-1
1.ExplaintheoperationprincipleofMOSFETusing
energy band diagrams inaccumulation,
depletion&inversionregions.
2.Derivetheexpressionofthresholdvoltageand
flatbandvoltage.
3.Derivetheexpressionofdraincurrentsinall
regionsofoperation(Cut-off,Linear&
Saturation).
4.Findtheexpressionoftransconductance.
5.DrawtheC~VcharacteristicsofMOSFET.
5 March 2024 VLSI Design 2

3. 5 March 2024 VLSI Design 35 March 2024 3
Chapter Coverage
Static Characteristics
Dynamic Characteristics

4. 5 March 2024 VLSI Design 4
Inverter

5. 5 March 2024 VLSI Design 5
Ideal Voltage Transfer
Characteristic (VTC)

6. 5 March 2024 VLSI Design 6
General Circuit Structure of
an nMOS Inverter

7. 5 March 2024 VLSI Design 7
Voltage Transfer
Characteristic (VTC)

8. 5 March 2024 VLSI Design 8
VTC
•ApplyingKirchhoff’sCurrentLaw
(KCL),theLoadcurrentisalways
equaltothenMOSdraincurrent.
I
D(V
in, V
out)=I
L(V
L)
•Twocriticalvoltagepoints(V
IL,V
IH)
definedonthisVTCcurve,wherethe
slopeoftheV
out(V
in)characteristic
becomesequalto-1.

9. 5 March 2024 VLSI Design 9
Critical Voltages
•V
OH:Maximum outputvoltagewhenthe
outputlevelislogic“1”.
•V
OL:Minimum output voltage when the
output level is logic “0”.
•V
IL:Maximum input voltage which can be
interpreted as logic “0”.
•V
IH:Minimum input voltage which can be
interpreted as logic “1”.
•V
TH:Threshold voltage of inverter, is
defined as the point, where V
in=V
out.

10. 5 March 2024 VLSI Design 10
Noise Immunity and Noise
Margins
•Theabilityofaninvertertointerpret
aninputsignalwithinavoltage
rangeaseitheralogic“0”orasa
logic“1”,allowsdigitalscircuitsto
operatewithacertaintoleranceto
externalsignalperturbations.

11. 5 March 2024 VLSI Design 11
Cascaded Inverters

12. 5 March 2024 VLSI Design 12
Noise Immunity and Noise
Margins

13. 5 March 2024 VLSI Design 13
Noise Margins

14. 5 March 2024 VLSI Design 14
Noise Margins
•Noisetolerancesfordigitalcircuits,
called,NoiseMargin(NM).
•NM
L=V
IL-V
OL :NoiseMarginLow
•NM
H=V
OH-V
IH:NoiseMarginHigh
•Thenoiseimmunityofthecircuit
increaseswithNM

15. 5 March 2024 VLSI Design 15
Resistive Load Inverter

16. 5 March 2024 VLSI Design 16
Resistive Load Inverter
•Calculation of V
OH:
V
out= V
DD–R
L.I
R , where (I
D=I
R)
•WhenV
inislow,i.e.,smallerthanthe
thresholdvoltageofthedriverMOSFET,
thedrivertransistoriscut-off.
•So I
D=I
R=0
•V
OH=V
DD

17. 5 March 2024 VLSI Design 17
Resistive Load Inverter
•Calculation of V
OL:
•I
R= I
DLinear
•(V
DD-V
OUT)/R
L= K
n/2[2(V
DD-V
TO).V
OL-V
OL
2
]

18. 5 March 2024 VLSI Design 18
Resistive Load Inverter
•Calculation of V
IL:
•I
R= I
DSaturation
•(V
DD-V
OUT)/R
L= K
n/2[(V
in-V
TO)
2
]

19. 5 March 2024 VLSI Design 19
Resistive Load Inverter
•Calculation of V
IH:
•I
R=I
DLinear
•(V
DD-V
out)/R
L=K
n/2[(V
in-V
TO).V
out-V
out
2
]
•Differentingbothsidesw.r.tV
inand
substitutingtheslope=-1

20. 5 March 2024 VLSI Design 20
Resistive Load Inverter

21. 5 March 2024 VLSI Design 21
Resistive Load Inverter

22. 5 March 2024 VLSI Design 22
Layout of Resistive Load
Inverter

23. 5 March 2024 VLSI Design 23
Enhancement-nMOS Load
Inverter

24. 5 March 2024 VLSI Design 24
Depletion-nMOS Load
Inverter

25. 5 March 2024 VLSI Design 25
Depletion-nMOS Load Inverter
Calculation of V
OH:
•When V
in is low, i.e., smaller than the
threshold voltage of the driver MOSFET,
the driver transistor is cut-off and does
not conduct any drain current.
•I
D,Driver, Cutoff=I
D,Load, Lin=0 A
•TheLoaddevicewhichoperatesinthe
linearregionalsohaszerodraincurrent.
•So I
D, Load=0 A
•Only valid solution in the linear region is
V
OH=V
DD

26. 5 March 2024 VLSI Design 26
Depletion-nMOS Load Inverter
Calculation of V
OL:
•I
D, Driver, Lin= I
D, Load, Sat
•I
D, Driver, Lin=(K
driver/2)[2(V
OH-V
TO).V
OL-V
OL
2
]
•I
D, Load, Sat=(K
Load/2)[-V
T, Load (V
OL)]
2

27. 5 March 2024 VLSI Design 27
Depletion-nMOS Load Inverter
Calculation of V
IL:
•I
D, Driver, Sat= I
D, Load, Lin
•I
D, Driver, Sat=(K
Driver/2)[V
in-V
TO]
2
•I
D, Load, Sat=(K
Load/2){2[V
T, Load (V
out)](V
DD-
V
out)-(V
DD-V
out)
2
}
•Differenting both sides w.r.t V
in and
substituting the slope=-1

28. 5 March 2024 VLSI Design 28
Depletion-nMOS Load Inverter
Calculation of V
IH:
•I
D, Driver, Lin= I
D, Load, Sat
•I
D, Driver, Lin=(K
Driver/2)[2(V
in-V
TO) V
out-
V
out
2
]
•I
D, Load, Sat=(K
Load/2)[-V
T, Load (V
out)]
2
•Differenting both sides w.r.t V
in and
substituting the slope=-1

29. 5 March 2024 VLSI Design 29
VTC of a Depletion-Load
Inverter Circuit

30. 5 March 2024 VLSI Design 30
VTC of Depletion-Load
Inverter Circuits

31. 5 March 2024 VLSI Design 31
Layout of Depletion-Load
Inverters

32. 5 March 2024 VLSI Design 32
CMOS Inverter

33. 5 March 2024 VLSI Design 33
VTC of CMOS Inverter

34. 5 March 2024 VLSI Design 34
Region of Operation
Region V
in V
out nMOS pMOS
A <V
T0,n V
OH Cut-Off Linear
B V
IL high≈V
O
H
Saturation Linear
C V
th V
th SaturationSaturation
D V
IH Low≈V
OL LinearSaturation
E >(V
DD+V
T0,p) V
OL Linear Cut-Off

35. 5 March 2024 VLSI Design 35
CMOS Inverter
Calculation of V
OH:
•WhenV
inislow,i.e.,smallerthanthe
thresholdvoltageofthedriverMOSFET,
thedrivertransistoriscut-offanddoes
notconductanydraincurrent.
•I
D,Driver, Cutoff=I
D,Load, Lin=0 A
•TheLoaddevicewhichoperatesinthe
linearregionalsohaszerodraincurrent.
•So I
D, Load=0 A
•Only valid solution in the linear region is
V
OH=V
DD

36. 5 March 2024 VLSI Design 36
CMOS Inverter
Calculation of V
OL:
•I
D, Driver, Lin= I
D, Load, Cut-off
•I
D, Driver, Lin=(K
driver/2)[2(V
DD-V
TO).V
OL-V
OL
2
]
•I
D, Load, Cut-off=0A
•V
OL=0 V

37. 5 March 2024 VLSI Design 37
CMOS Inverter
Calculation of V
IL:
•I
D, nMOS, Sat= I
D, pMOS, Lin
•I
D, nMOS, Sat=(K
n/2)[V
GS,n-V
TO,n]
2
•I
D, pMOS, Lin=(K
P/2)[2(V
GS,p-V
TO,p)V
DS,p-V
DS,p)
2
]
•Differenting both sides w.r.t V
in and
substituting the slope=-1
•V
IL=(2V
out+ V
TO,p-V
DD+ K
R
V
TO,n)/(1+K
R)
•Transconductance Ratio(K
R)
•K
R =K
n/K
P

38. 5 March 2024 VLSI Design 38
CMOS Inverter
Calculation of V
IH:
•I
D, Driver, Lin= I
D, Load, Sat
•I
D, nMOS, Lin= (K
n/2)[2(V
GS,n-V
TO,n)V
DS,n-V
DS,n)
2
]
•I
D, pMOS, Sat=(K
p/2)[V
GS,p-V
TO,p]
2
•Differenting both sides w.r.t V
in and
substituting the slope=-1
•V
IH=(V
DD+V
TO,p+K
R (2V
out+V
TO,n))/(1+K
R)
•Transconductance Ratio(K
R)
•K
R =K
n/K
P

39. 5 March 2024 VLSI Design 39
CMOS Inverter
Calculation of V
th:
•I
D, Driver, Sat= I
D, Load, Sat
•I
D, nMOS, Sat= (K
n/2)[2(V
GS,n-V
TO,n)
2
]
•I
D, pMOS, Sat=(K
p/2)[V
GS,p-V
TO,p]
2
•V
th=V
TO,n+K
R
-1/2
(V
DD+V
TO,p)/(1+K
R
-1/2
)
•Transconductance Ratio(K
R)
•K
R=K
n/K
P

40. 5 March 2024 VLSI Design 40
Design of CMOS Inverter

41. 5 March 2024 VLSI Design 41
Design of CMOS Inverter
•CMOS inverterdoesn’tdraw any
significantcurrentfrompowersupply,
exceptforsmallleakageandsub-
thresholdcurrents.
•Thesecurrentsexistwheninputvoltageis
eithersmallerthanV
TO,norlargerthan
(V
DD+V
TO,p)repectively.
•ThenMOSandpMOStransistorsconducta
non-zerocurrent,duringlow-to-highand
high-to-lowtransitions,i.e.inRegionsB,
C,D.

42. 5 March 2024 VLSI Design 42
Design of CMOS Inverter
•Thecurrentdrawnfromthepowersupply
duringtransitionreachesitspeakvalue
whenV
in=V
th.
•Inotherwords,themaximum currentis
drawnwhenbothtransistorsareoperating
insaturationmode.
•VTCofaCMOSinverterandthepower
supplycurrent,asafunctionoftheinput
voltage,isshown.

43. 5 March 2024 VLSI Design 43
VTC & Power Supply Current
of a CMOS Inverter

44. 5 March 2024 VLSI Design 44
•ThethresholdvoltageV
thisidentifiedas
oneofhemostimportantparameterthat
characterizethesteady-stateinput-output
behavioroftheCMOSinvertercircuit.
•TheCMOSinverter,providesafulloutput
voltageswingbetween0andV
DDand
thereforethenoisemargins(NM)are
relativelywider.
•So,theproblemofdesigningaCMOS
invertercanbereducedtosettingthe
inverterthreshold(V
th)toadesired
voltagevalue.
Design of CMOS Inverters

45. 5 March 2024 VLSI Design 45
•Switchingthresholdvoltageofan
idealinverteris,V
th,ideal=V
DD/2.
•TheInverterthresholdvoltageV
th
shiftstolowervalueswithincreasing
K
Rratio.
•ForasymmetricCMOSinverterwith
V
T0,n=V
T0,pandK
R=1.
•V
IL=1/8(3V
DD+2V
T0,n)
•V
IH=1/8(5V
DD-2V
T0,n)
Design of CMOS Inverters

46. 5 March 2024 VLSI Design 46
•ForasymmetricCMOSinverterwith
V
IL+V
IH=V
DD
•ThenoisemarginsNM
LandNM
Hfor
thissymmetricCMOSinverterare
nowcalculatedas:
•NM
L=V
IL-V
OL=V
IL
•NM
H=V
OH-V
IH=V
DD-V
IH
•NM
L=NM
H=V
IL
Design of CMOS Inverters

47. 5 March 2024 VLSI Design 47
Design of CMOS Inverters

48. 5 March 2024 VLSI Design 48
Supply Voltage Scaling in
CMOS Inverters
V
DD
min
=V
T0,n+ V
T0,p

49. 5 March 2024 VLSI Design 49
VTC of CMOS Inverter at
Lower V
DD
min

50. 5 March 2024 VLSI Design 50
Layout of CMOS Inverter

51. 5 March 2024 VLSI Design 51
Design of D-nMOS Load
Inverter

52. 5 March 2024 VLSI Design 52
Layout Design

53. 5 March 2024 VLSI Design 53
Design of E-nMOS Load
Inverter

54. 5 March 2024 VLSI Design 54
Design

55. 5 March 2024 VLSI Design 555 March 2024 555 March 2024 VLSI Design 55
VLSI Design
Switching Characteristics of
MOS Inverters

56. 5 March 2024 VLSI Design 56
Parasitic Capacitances

57. 5 March 2024 VLSI Design 57
Load Capacitance

58. 5 March 2024 VLSI Design 58
Rise Time -Fall Time

59. 5 March 2024 VLSI Design 59
Rise Time -Fall Time

60. 5 March 2024 VLSI Design 60
Charge Up

61. 5 March 2024 VLSI Design 61
Charge Up

62. 5 March 2024 VLSI Design 62
CMOS Inverter

63. 5 March 2024 VLSI Design 63
Layout Design

64. 5 March 2024 VLSI Design 64
Ring Osci

65. 5 March 2024 VLSI Design 65
Output Waveforms

66. 5 March 2024 VLSI Design 66
Interconnect

67. 5 March 2024 VLSI Design 67
Interconnect

68. 5 March 2024 VLSI Design 68
Typical Graph

69. 5 March 2024 VLSI Design 69

70. 5 March 2024 VLSI Design 70
Multi Level Metallization

71. 5 March 2024 VLSI Design 71
Current Density

72. 5 March 2024 VLSI Design 72
Capacitances

73. 5 March 2024 VLSI Design 73
Fringe Capacitance

74. 5 March 2024 VLSI Design 74
Graph

75. Calculation of Interconnect
Delay
•RC Delay Models
–Aninterconnectlinecanbemodeledas
alumpedRCnetworkifthetimeof
flightacrosstheinterconnectionlineis
significantlyshorterthanthesignal
rise/falltimes.
–Thisisusuallythecaseinmoston-chip
interconnects.
5 March 2024 VLSI Design 75

76. RC Delay Models
•Assuming thatthecapacitance is
dischargedinitially,andassumingthatthe
inputsignalisarisingsteppulseattimet
=0,theoutputvoltagewaveformofthis
simpleRCcircuitisfoundas
•Therisingoutputvoltagereachesthe
50%-pointatt=T
PLH,thus,wehave
5 March 2024 VLSI Design 76

77. RC Delay Models
•Thepropagationdelayforthesimple
lumpedRCnetworkisfoundas
•TheaccuracyofthesimplelumpedRC
modelcanbesignificantlyimprovedby
dividingthetotallineresistanceintotwo
equalparts(theT-model)
5 March 2024 VLSI Design 77

78. RC Delay Models
•Thetransientbehaviorofaninterconnect
linecanbemoreaccuratelyrepresented
usingtheRCladdernetwork,asshown.
•Here,eachRC-segmentconsistsofa
seriesresistance(R/N),andacapacitance
(C/N)connectedbetweenthenodeand
theground.
5 March 2024 VLSI Design 78

79. RC Delay Models
•Itcanbeexpectedthattheaccuracyof
thismodelincreaseswithincreasingN,
wherethetransientbehaviorapproaches
thatofadistributedRClineforverylarge
valuesofN.
5 March 2024 VLSI Design 79

80. The Elmore Delay
•Consider a general RC tree network.
–There are no resistor loops in this circuit
–All of the capacitors in an RC tree are
connected between a node and the
ground.
–There is one input node in the circuit.
–There is an unique path resistive path
from the input node to any other node
in the circuit.
5 March 2024 VLSI Design 80

81. The Elmore Delay
•Assumingthattheinputsignalisastep
pulseattimet=0andtheElmoredelay
atnodeiofthisRCtreeisgivenbythe
followingexpression.
5 March 2024 VLSI Design 81

82. The Elmore Delay
•the Elmore delay at node 7 can be
found as
•Similarly, the Elmore delay at node 5
can be calculated as
5 March 2024 VLSI Design 82

83. The Elmore Delay
5 March 2024 VLSI Design 83
•AsaspecialcaseofthegeneralRCtree
network,considernowthesimpleRC
laddernetworkasshown.
•Here,theentirenetworkconsistsofone
singlebranch,andtheElmoredelayfrom
theinputtotheoutput(nodeN)isfound
as:

84. The Elmore Delay
•IfwefurtherassumeanuniformRCladder
network,consistingofidenticalelements
of(R/N)and(C/N)thentheElmoredelay
fromtheinputtotheoutputnode
becomes:
•ForverylargeN(distributedRCline
behavior),thisdelayexpressionreduces
to:
5 March 2024 VLSI Design 84

85. The Elmore Delay
•Thus,thepropagationdelayofa
distributedRClineisconsiderablysmaller
thanthatofalumpedRCnetwork.
•Ifthelengthoftheinterconnectionlineis
sufficientlylargeandtherise/falltimesof
thesignalwaveformsarecomparableto
thetimeofflightacrosstheline,thenthe
interconnectlinemustbemodeledasa
transmissionline.
5 March 2024 VLSI Design 85

86. Switching Power Dissipation of
CMOS Inverters
•Asdiscussedthestaticpower
dissipationoftheCMOSinverteris
quitenegligible.
•The dynamic power consumption of
the CMOS inverter is derived.
5 March 2024 VLSI Design 86

87. •Duringswitchingeventstheoutput
loadcapacitanceisalternatively
chargedupandchargeddown.
5 March 2024 VLSI Design 87
Dynamic Power Dissipation Analysis

88. •TheoutputloadcapacitanceC
loadis
beingchargedupthroughthepMOS
transistor;therefore,thecapacitor
currentequalstheinstantaneous
draincurrentofthepMOStransistor.
•Theaveragepowerdissipatedbythe
inverteroveroneperiodcanbe
foundas:
5 March 2024 VLSI Design 88
Dynamic Power Dissipation Analysis

89. Dynamic Power Dissipation Analysis
•Typicalinputandoutputvoltagewaveforms
andthecapacitorcurrentwaveformduring
switchingoftheCMOSinverter.
5 March 2024 VLSI Design 89

90. •Sinceduringswitching,thenMOS
transistorandthepMOStransistorina
CMOSinverterconductcurrentforone-
halfperiodeach.
•Theaveragepowerdissipationofthe
CMOSinvertercanbecalculatedasthe
powerrequiredtochargeupandcharge
downtheoutputloadcapacitance.
5 March 2024 VLSI Design 90
Dynamic Power Dissipation Analysis

91. •Evaluating the integrals, we obtain
•Theaveragepowerdissipationofthe
CMOS inverterisproportionaltothe
switchingfrequency“f”.
5 March 2024 VLSI Design 91
Dynamic Power Dissipation Analysis

92. Summary
•Therefore,thelow-poweradvantageofCMOS
circuitsbecomeslessprominentinhigh-speed
operation,wheretheswitchingfrequencyis
high.
•Alsonotethattheaveragepowerdissipation
isindependentofalltransistorcharacteristics
andtransistorsizes.
•Consequently,theswitchingdelaytimeshave
norelevancetotheamountofpower
consumptionduringtheswitchingevents.
•switchingpowerissolelydissipatedfor
charginganddischargingtheoutput
capacitancefromV
OLtoV
OH,andviceversa.
5 March 2024 VLSI Design 92

93. Summary
•Theswitchingpowerexpressionderived
fortheCMOSinverteralsoappliestoall
generalCMOScircuits.
5 March 2024 VLSI Design 93

94. Power-Delay Product
•Thepower-delayproduct(PDP)isa
fundamentalparameterwhichisoften
usedformeasuringthequalityandthe
performanceofaCMOSprocessandgate
design.
•Asaphysicalquantity,thepower-delay
productcanbeinterpretedasthe
averageenergyrequiredforagateto
switchitsoutputvoltagefromlowtohigh
andfromhightolow.
•Theamountofenergyrequiredtoswitch
theoutput.
5 March 2024 VLSI Design 94

95. Power-Delay Product
•Fromadesignpoint-of-view,itisdesirable
tominimizethepower-delayproduct.
•SincethePDPisafunctionoftheoutput
loadcapacitanceandthepowersupply
voltage,thedesignershouldtrytokeep
bothC
loadandV
DDassmallaspossible
whendesigningaCMOSlogicgate.
•where istheaverageswitchingpower
dissipationatmaximum operating
frequencyand istheaverage
propagationdelay.
5 March 2024 VLSI Design 95p
 *
avg
p

96. Power-Delay Product
•Thefactorof2accountsfortwo
transitionsoftheoutput,fromlowtohigh
andfromhightolow.
5 March 2024 VLSI Design 96

97. 5 March 2024 VLSI Design 975 March 2024 975 March 2024 97
VLSI Design
Combinational Logic
Circuits

98. 5 March 2024 VLSI Design 98
Combinational Logic Circuit

99. 5 March 2024 VLSI Design 99
NOR Gate using Depletion
type Load

100. Critical Voltages
•Calculation of V
OH
–The solution of this equation gives
V
OH= V
DD.
•Calculation of V
OL
–Three cases must be considered
5 March 2024 VLSI Design 100

101. Critical Voltages
•In case (i), where the driver transistor A is
on, the ratio is
•Incase(ii),wherethedrivertransistorB
ison,theratiois
•TheoutputlowvoltagelevelV
OLinboth
casesisfoundas:
5 March 2024 VLSI Design 101

102. Critical Voltages
•ifthe(W/L)ratiosofbothdriversare
identical,i.e.,(W/L)
A=(W/L)
Btheoutput
lowvoltage(V
OL)valuescalculatedfor
case(i)andcase(ii)willbeidentical.
•Incase(iii),wherebothdrivertransistors
areturnedon,thesaturatedloadcurrent
isthesumofthetwolinear-modedriver
currents.
5 March 2024 VLSI Design 102

103. Critical Voltages
•Sincethegatevoltagesofbothdrivertransistors
areequal(V
A=V
B=V
OH),wecandevisean
equivalentdriver-to-loadratiofortheNOR
structure:
•TheNORgatewithbothofitsinputstiedtoa
logic-highvoltageisreplacedwithannMOS
depletion-loadinvertercircuitwiththedriver-to-
loadratio(K
R)havingoutputvoltagelevel:
5 March 2024 VLSI Design 103

104. 5 March 2024 VLSI Design 104
Generalized NOR Structure with
Multiple Inputs

105. Generalized NOR Structure
•The combined pull-down current can then be
expressed as
•Assumingthattheinputvoltagesofalldriver
transistorsareidenticalandV
GSk=V
GSfor
k=1,2,...,n.Then thepull-down current
expressioncanberewrittenas
5 March 2024 VLSI Design 105

106. Generalized NOR Structure
•Thus,themultiple-inputNORgatecan
alsobereducedtoanequivalentinverter
forstaticanalysis.The(W/L)ratioofthe
drivertransistorhereis
5 March 2024 VLSI Design 106

107. 5 March 2024 VLSI Design 107
Transient Analysis of NOR Gate

108. 5 March 2024 VLSI Design 108
Two-Input NAND Gate using
Depletion type Load

109. 5 March 2024 VLSI Design 109
NAND Gate using Depletion Load

110. Two-Input NAND Gate
•Consider the NAND2 gate with both of its
inputs equal to V
OH.
•The drain currents of all transistors in the
circuit are equal to each other.
•Neglecting the substrate-bias effect for
driver transistor A for simplicity, we get
5 March 2024 VLSI Design 110

111. Two-Input NAND Gate
•The drain-to-source voltages of both
driver transistors can be
•Letthetwodrivertransistorsbeidentical,
i.e.,k
driverA=k
driverB=k
driver
•TheoutputvoltageV
OLisequaltothesum
ofthedrain-to-sourcevoltagesofboth
drivers.
5 March 2024 VLSI Design 111

112. Two-Input NAND Gate
•Thefollowinganalysisgivesabetterand
moreaccurateviewoftheoperationof
twoseries-connecteddrivertransistors.
•Now consider the two identical
enhancement-typenMOStransistorswith
their-gateterminalsconnectedandV
TA=
V
TB=V
T0.
•SinceI
DA=I
DB,thiscurrentcanalsobe
expressedas
5 March 2024 VLSI Design 112

113. Two-Input NAND Gate
•Using V
GSA= V
GSB-V
DSB
•Now let V
GS= V
GSBand V
DS= V
DSA+ V
DSB.
The drain-current expression can then be
written as follows.
•Thus,twonMOStransistorsconnectedin
seriesandwiththesamegatevoltage
behavelikeonenMOStransistorwithk
eq
=0.5k
driver.
5 March 2024 VLSI Design 113

114. Generalized NAND Structure with
Multiple Inputs
•n-series-connected drivertransistors,
assumingthatthethresholdvoltagesofall
transistorsareequaltoV
T0.
•Hence,the(W/L)ratiooftheequivalent
drivertransistoris
5 March 2024 VLSI Design 114

115. Two-Input NAND Gate
•Iftheseries-connectedtransistorsare
identical,i.e.,(W/L)
1=(W/L)
2=...=
(W/L),thewidth-to-lengthratioofthe
equivalenttransistorbecomes
5 March 2024 VLSI Design 115

116. 5 March 2024 VLSI Design 116
n-input NAND Gate using
Depletion Load

117. 5 March 2024 VLSI Design 117
Transient Analysis of NAND Gate

118. Transient Analysis of NAND Gate
•Assume,forexample,thattheinputV
Aisequal
toV
OHandtheotherinputV
Bisswitchingfrom
V
OHtoV
OL.Inthiscase,boththeoutputvoltage
V
out,andtheinternalnodevoltageV
xwillrise,
resultingin
•Initsreversecase
5 March 2024 VLSI Design 118

119. 5 March 2024 VLSI Design 119
CMOS Network

120. 5 March 2024 VLSI Design 120
A CMOS NOR Gate with Inverter
Equivalent 
n
p
pTDD
n
p
nT
th
k
k
VV
k
k
V
NORV
4
1
4
)2(
,,




121. 5 March 2024 VLSI Design 121
Dynamic Characteristics of
NOR Gate

122. 5 March 2024 VLSI Design 122
Layout Design of NOR Gate

123. 5 March 2024 VLSI Design 123 
n
p
pTDD
n
p
nT
th
k
k
VV
k
k
V
NANDV
21
2
)2(
,,



A CMOS NAND Gate with Inverter
Equivalent