Lecture notes for the Digital VLSI Design

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1. ____________________________________________________________ Interconnect Capacitance Design Data Wire area and fringe capacitance values for typical 0.25 μ m CMOS process. The table rows represent the top plate of the capacitor, the columns the bottom plate. The area capacitances are expressed in aF / μ m 2 , while the fringe capacitances (given in the shaded rows) are in aF / μ m

2. ____________________________________________________________ Interconnect Capacitance Design Data Inter-wire capacitance per unit wire length for different interconnect layers of typical 0.25 μ m CMOS process. The capacitances are expressed in aF / μ m , and are for minimally-spaced wires. Q1: - Some global signals, such as clocks, are distributed all over the chip. The length of those wires can be substantial. For die sizes between 1 and 2 cm, wires can reach a length of 10 cm and have associated wire capacitances of substantial value . Consider an aluminum wire of 10 cm long and 1 mm wide, routed on the first Aluminum layer. We can compute the value of the total capacitance using the data presented in Table 4.2.

3. The resistance of a wire is proportional to its length L and inversely proportional to its cross-section area A . Since H is the constant for the given technology w here ρ is the resistivity of the material (in Ω - m). ; Units, Ω /❑ (Ohm-per-square) Sheet resistance of the material The resistance of a square conductor is independent of its absolute size. To obtain the resistance of a wire, simply multiply the sheet resistance by its ratio (L/W). ____________________________________________________________ Resistance

4. ____________________________________________________________ Resistance Material ρ ( Ω -m) Silver (Ag) 1.6 ×10 -8 Copper (Cu) 1.7 ×10 -8 Gold (Au) 2.2 ×10 -8 Aluminum 2.7 ×10 -8 Tungsten (W) 5.5 ×10 -8 Resistivity of commonly-used Conductors (at 20 C). Material Sheet Resistance ( Ω /❑) n- or p- well diffusion 1000-1500 n + , p + diffusion 50-150 n + , p + diffusion with silicide 3-5 n + , p + polysilicon 150-200 n + , p + polysilicon with silicide 4-5 Aluminum 0.05-0.1 Sheet resistance values for a typical 0.25 μ m CMOS process. polycide Silicide: WSi2, TiSi2 , PtSi2 , and TaSi . WSi2 , has a resistivity ρ of 130 μ Ω -cm .

5. ____________________________________________________________ Resistance Transitions between routing layers add extra resistance to a wire, called the contact resistance . Reduce the contact resistance by making the contact holes larger. Current tends to concentrate around the perimeter in a larger contact hole and this effect is called current crowding . The contact resistances are typical for via’s (metal-to-metal contacts) of a 0.25 μ m CMOS process : F or metal or polysilicon to n + , p + : 5-20 Ω For metal to polysilicon: 1-5 Ω The resistance of a semiconductor wire to be linear and constant at low frequency. At very high frequencies, the “ skin effect” — comes into play such that the resistance becomes frequency-dependent . High-frequency currents tend to flow primarily on the surface of a conductor with the current density falling off exponentially with depth into the conductor. The skin depth, δ is defined as the depth where the current falls off to a value of e -1 of its nominal value, and is given by δ =   f : frequency of the signal μ = 4 π× 10 -7 H/m: permeability in free space

6. ____________________________________________________________ Resistance For Aluminum at 1 GHz, the skin depth is equal to 2.6 μ m . The effect can be approximated by assuming that the current flows uniformly in an outer shell of the conductor with thickness δ. Overall cross-section of the wire: . The resistance (per unit length) at high frequencies ( f > f s ): If ; this may cause an extra attenuation — and hence distortion — of the signal being transmitted over the wire.. To determine the skin-effect, we can find the frequency f s where the skin depth is equal to half the largest dimension (W or H) of the conductor. Below f s the whole wire is conducting current , and the resistance is equal to (constant) low-frequency resistance of the wire. Hence, the value of f s :  

7. ____________________________________________________________ Resistance Q2:- Consider again the aluminum wire, which is 10 cm long and 1 μ m wide, and is routed on the first Aluminum layer. Assuming a sheet resistance for Al1 of 0.075 Ω / ❑, find total resistance of the wire. Q3:-

8. ____________________________________________________________ Electrical Wire Models Ideal Wire:- Simple lines with no attached parameters or parasitic. These wires have no impact on the electrical behavior of the circuit. A voltage change at one end of the wire propagates immediately to its other ends, even if those are some distance away . Lumped Model:- The circuit parasitic of a wire are distributed along its length. If only single parasitic parameter dominant then the distributed parameter can be used as a lumped element. The effects of the parasitic can be described by an ordinary differential equation . When the resistive component of the wire is small and the switching frequencies are in the low to medium range, it is meaningful to consider only the capacitive component of the wire, and to lump the distributed capacitance into a single capacitor c wire C lumped = L×c wire L

9. ____________________________________________________________ Electrical Wire Models Question:- For the circuit of Figure shown, assume that a driver with a source resistance of 10 k Ω is used to drive a 10 cm long, 1 μ m wide Al1 wire. Consider total lumped capacitance for this wire equals 11 pF . Find the V out w hen applying a step input (with V in going from 0 to V)

10. ____________________________________________________________ Electrical Wire Models Lumped RC model:- L umps the total wire resistance of each wire segment into one single R and similarly combines the global capacitance into a single capacitor C . This simple model, called the lumped RC model . RC Tree:- Properties of RC Tree: The network has a single input node called ‘s’. All the capacitors are between a node and the ground. The network does not contain any resistive loops (which makes it a tree)

11. ____________________________________________________________ Time Constant Calculation (Elmore delay) Path resistance R ii :- Total resistance of an unique resistive path between the source node ‘ s’ and any node ‘ i ’ of the network. For example:- The path resistance between the source node ‘ s’ and node ‘4’. Shared path resistance R ik :- The resistance shared among the paths from the root node ’s’ to nodes ‘k’ and ‘ i ’ . For example : The Elmore delay (equivalent to the first order time constant of the network) at node ‘ i ’ is then given by

12. ____________________________________________________________ Time Constant Calculation (Elmore delay) RC chain (or ladder ) network:- Approximate model of a resistive-capacitive wire. The Elmore delay of the above network R ii is shared path

13. ____________________________________________________________ Time Constant Calculation (Elmore delay) Question: - Calculate the time constant of the ladder network shown in the figure. Consider R 1 = R 2 = -- = R i , C 1 = C 2 = --- = C i , and length of wire is L. Each section of wire has resistance R= rL /N, and C= cL /N .

14. ____________________________________________________________ Distributed rc Line Distributed rc Line:- The voltage at node i ; for Diffusion Equation where V is the voltage at a particular point in the wire, and x is the distance between this point and the signal source.

15. ____________________________________________________________ Distributed rc Line Distributed rc Line:- Diffusion Equation Approximate solution of the above equation The response of a wire to a step input Step waveform “ diffuses ” from the start to the end of the wire, and the waveform rapidly degrades, resulting in a considerable delay for long wires.

16. ____________________________________________________________ Distributed rc Line Step response of lumped and distributed RC networks—points of Interest. Q1:- Consider again the aluminum wire, which is 10 cm long and 1 μ m wide, and is routed on the first Aluminum layer. Assuming a sheet resistance for Al1 of 0.075 Ω / ❑ and lumped capacitance for this wire equals 11 pF , find the propagation delay of the wire.

17. ____________________________________________________________ Design Rules of Thumb rc delays should only be considered when t pRC >> t pgate of the driving gate. rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line.

18. ____________________________________________________________ Distributed rc Line Step response of lumped and distributed RC networks—points of Interest. Q1:- Consider again the aluminum wire, which is 10 cm long and 1 μ m wide, and is routed on the first Aluminum layer. Assuming a sheet resistance for Al1 of 0.075 Ω / ❑ and lumped capacitance for this wire equals 11 pF , find the propagation delay of the wire.

19. ____________________________________________________________ Transmission Line When the signal frequency applied to the circuit becomes sufficiently high, the inductance of the wire begins to dominate the delay behavior , and transmission line effects have to be considered . With the advent of Copper interconnect and the high switching speeds enabled by the deep-submicron technologies, transmission line effects are soon to be considered in the fastest CMOS designs . Similar to the resistance and capacitance of an interconnect line, the inductance is distributed over the wire. A distributed rlc model of a wire, known as the transmission line model , becomes the most accurate approximation of the actual behavior. The transmission line has the prime property that a signal propagates over the interconnection medium as a wave . In the wave mode , a signal propagates by alternatively transferring energy from the electric to the magnetic fields , or equivalently from the capacitive to the inductive modes .

20. ____________________________________________________________ Transmission Line Wave Propagation E quation:- Consider the point x along the transmission line at time t Assuming that the leakage conductance g equals 0, which is true for most insulating materials.

21. ____________________________________________________________ Transmission Line The Lossless Transmission Line:- assume that the resistance of the line is small. Ideal wave equation W ave speed: Even though the values of both l and c depend on the geometric shape of the wire, their product is a constant and is only a function of the surrounding media. The propagation delay per unit wire length ( t p ):

22. ____________________________________________________________ Transmission Line Wave propagation along lossless transmission line . V capacitance cdx must be charged for the wave to propagate over an additional distance dx dx Initial current I is zero to right of x Characteristics impedance of transmission line Characteristics impedance is a function of the dielectric medium and the geometry of the conducting wire and isolator, and is independent of the length of the wire and the frequency.

23. ____________________________________________________________ Transmission Line Termination Termination:- The termination determines how much of the wave is reflected upon arrival at the wire end. Reflection coefficient ( ρ ) :- is the ratio of reflected voltage ( V refl ) wave to the incident voltage wave ( V inc ) at the end of Transmission line. ; R is the termination Resistance The total voltages and currents at the termination end are the sum of incident and reflected waveforms.

24. ____________________________________________________________ Transmission Line Termination Case 1:- Terminating resistance is equal to the characteristics impedance, R = Z 0, ρ = 0 , No reflection from terminating end. transmission line seems to be infinite extension of the line.

25. ____________________________________________________________ Transmission Line Termination Case 2:- Terminating resistance is an open circuit, R = ∞ (Open circuit) , ρ = 1 , Complete reflection of the waveform from terminating end with 0 degree of phase shift.  

26. ____________________________________________________________ Transmission Line Termination Case 3:- Terminating resistance is a short circuit, R = 0 (short circuit) , ρ = -1 , Complete reflection of the waveform from terminating end with 180 degree of phase shift.  

27. ____________________________________________________________ Transmission Line Termination The transient behavior of a complete transmission line can now be examined. It is influenced by the characteristic impedance of the line, the series impedance of the source Z S , and the loading impedance Z L at the destination end. V in V source   Consider the Case 1 of the terminating behaviour of transmission line. i.e. Z L = ∞, open circuit; Reflection coefficient, ρ L = 1

28. ____________________________________________________________ Transmission Line Termination V in V source = 0.83 V   Case I : Large source resistance, Z s = 5Z , V in = 5V This signal reaches the end of the line after L/v sec, where L stands for the length of the wire. At the destination end (load) the voltage double after reflection of the waveform. V dest = 1.66 V t ime –of- flight :- The time it takes for the wave to propagate from one end of the wire to other end. t flight = L/v

29. ____________________________________________________________ Transmission Line Termination   The voltage amplitude at source and destination nodes gradually reaches its final value of V in . The overall rise time is, however, many times L/v. V in V source The incident waveform is reflected with an amplitude determined by the source reflection coefficient, ρ s

30. VLSI Design Methodology

31. Introduction The structural complexity of digital integrated circuits has been increasing at an exponential rate over the last 30 years. This phenomenal growth rate has been sustained primarily by the constant advances in manufacturing technology, as well as by the increasing need for integrating more complex functions on chip. The demands of the rapidly rising chip complexity has created significant challenges in many areas; practically hundreds of team members are involved in the development of a typical VLSI product, including the development of technology, computer-aided design (CAD) tools, chip design, fabrication, packaging, testing and reliability qualification. The efficient organization of these efforts under a well-structured system design methodology is essential for the development of economically viable VLSI products, in a timely manner. Complexity and Productivity Growth Complexity grows 58%/year (doubles every 18 months). Productivity grows 21%/year (doubles every 3 ½ year).

32. VLSI Technology and Device Driver Less Power Consumption Less price/More economical More or Less components per board Higher reliability Improved interconnect More compactness High speed of operation Less manufacturing cost

33. VLSI Design: Overview Performance vs Design Cycle Technology Window full-custom design style requires a longer time until design maturity can be reached, yet the inherent flexibility of adjusting almost every aspect of circuit design allows far more opportunity for circuit performance improvement during the design cycle. A semi-custom design style (such as standard-cell based design or FPGA) will allow a shorter design time until design maturity can be achieved.

34. VLSI Design Flow Integrated circuit can be described by three different domain: Behavioral domain:- The behavioral domain specifies what we wish to accomplish with a system. For instance, at the highest level, we might want to build an ultra-low-power radio for a distributed sensor network. Structural domain:- The structural domain specifies the interconnection of components required to achieve the behavior we desire. Physical domain:- physical domain specifies how to arrange the components in order to connect them, which in turn allows the required behavior. These domains can further be hierarchically divided into different levels of design abstraction . Architectural or functional level Logic or Register Transfer level (RTL) Circuit level

35. VLSI Design Flow The Y-chart (first introduced by D. Gajski ) illustrates a design flow for most logic chips, using design activities on three different axes (domains) which resemble the letter "Y." Architectural level RTL level Circuit level

36. VLSI Design Flow Verification is essential at every step during the process

37. VLSI Design Technology Full Custom Design : Full Custom Design involves creating and verifying all components of a chip from the transistor level upward. This meticulous process allows for precise optimization of speed, power, and area, making it ideal for mass production. However, it comes with a trade-off — the design and production time of full custom designs are typically longer compared to semi-custom designs. Advantages of Full Custom Design: Optimized performance:  Full custom designs can achieve higher performance levels compared to semi-custom designs. Area efficiency:  By tailoring every component, full custom designs can minimize chip area. Power optimization:  Fine-grained control over individual components enables power optimization. Disadvantages of Full Custom Design: Longer design and production time:  Designing and verifying each component from scratch can be time-consuming. Not cost-efficient for small-scale projects:  The high upfront investment in design and fabrication makes full custom design less suitable for low-volume productions.

38. VLSI Design Flow Semi Custom Design : Semi-Custom Design offers a compromise between design flexibility and time-to-market constraints. In this methodology, pre-designed and pre-tested modules are used, with the option to customize and add additional components as needed. While it reduces design time, it may not be as optimized or cost-efficient for mass production compared to full custom design. Advantages of Semi-Custom Design: Reduced design time:  Leveraging pre-designed modules accelerates the design process. Flexibility :  Additional components can be integrated to meet specific requirements without starting from scratch. Suitable for low-volume productions:  Semi-custom design offers a balance between customization and cost-effectiveness for smaller-scale projects . Disadvantages of Semi-Custom Design: Limited optimization:  Pre-designed modules may not offer the same level of performance optimization as full custom designs. Higher production time:  Despite faster design time, integrating and customizing modules can extend the overall production time.

39. VLSI Design Technology

40. Field Programmable Gate Array (FPGA) Field programmable gate array (FPGA) chip consists: I/O blocks Configurable logic blocks (CLBs) Programmable interconnect Configurable switch matrices FPGA chips containing thousands or even more, of logic gates The programming of the interconnects is accomplished by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. The signal routing between the CLBs and the I/O blocks is accomplished by setting the configurable switch matrices accordingly.

41. Configurable Logic Block (CLB) of FPGA Look up Table Configurable Logic Blocks contain the logic for the FPGA . In a large grain architecture, these CLBs will contain enough logic to create a small state machine . In a fine grain architecture, the CLB will contain only very basic logic. It contains RAM for creating arbitrary combinatorial logic functions. It also contains flip-flops for clocked storage elements, and multiplexers in order to route the logic within the block and to and from external resources. The muxes also allow polarity selection and reset and clear input selection.

42. Programmable Interconnects of FPGA There are long lines which can be used to connect critical CLBs that are physically far from each other on the chip without inducing much delay. They can also be used as buses within the chip. are also short lines which are used to connect individual CLBs which are located physically close to each other. There is often one or several switch matrices, like that in a CPLD, to connect these long and short lines together in specific ways. Programmable switches inside the chip allow the connection of CLBs to interconnect lines and interconnect lines to each other and to the switch matrix. Three-state buffers are used to connect many CLBs to a long line, creating a bus.

43. Configurable Logic Block (CLB) of FPGA Examples of SRAM based FPGA families include the following: Altera FLEX family Atmel AT6000 and AT40K families Lucent Technologies ORCA family Xilinx XC4000 and Virtex families