Lecture5 Chapter4- Design Decimal Adder and Binary Multiplier Circuits.pdf

dld lecture

1. Chapter4: Combinational Logic
Lecture5-Design Decimal Adder and Binary Multiplier Circuits
Engr. Arshad Nazir, Asst Prof
Dept of Electrical Engineering
SEECS 1Fall 2022

2. Objectives
•DesignDecimalAdderandBinaryMultiplierCircuits
2Fall 2022

3. Decimal Adder
•Computersorcalculatorsthatperformarithmeticoperationsdirectly
inthedecimalnumbersystemrepresentdecimalnumberinbinary
codedform(BCD).
•Anadderforsuchacomputermustemployarithmeticcircuitsthat
acceptbinarycodeddecimalnumbersandpresentresultsinthesame
code
•ToaddtwoBCDdigits,werequire
9inputs:eightinputsfortwoBCDsandonecarry-in.Sincefour
bitsarerequiredtocodeeachdecimaldigit
5outputs:fouroutputsforoneBCDandonecarry-out
3Fall 2022

4. BCD Adder
•TodesignaBCDadderwerequireatruthtablewith2^9entries(since9
inputs).Thismaybecometoodifficulttoworkwithsowedevicesome
easyalternativetodesignaBCDadder.Thisisshownintable4-5
•Eachdigitdoesn’texceed9andsotheoutputsumcan’texceed,9+9+1=
19(twoBCDdigitsandinputcarry)
•SupposeweapplytwoBCDdigitstoa4-bitbinaryadder
•Theadderwillformthesuminbinaryandproducesaresultthatranges
from0through19
•Thesebinarynumbersarelistedintable4-5andarelabeledbysymbols
K,Z
8,Z
4,Z
2andZ
1.(Kistheoutputcarry).Buttheoutputsummustbe
representedinBCD(notbinary)andshouldappearintheformlistedin
thecolumnsC,S
8,S
4,S
2andS
1underBCDsum
•Theproblemistofindarulebywhichbinarysumisconvertedto
correspondingBCDsum
4Fall 2022

5. 5Fall 2022

6. Correction for BCD Adder
•Fromthetableitisapparentthatwhenbinarysumisequaltoorless
than1001(decimal9),thecorrespondingBCDnumberisidenticaland
thereforenocorrectionisneeded.
•Modificationsareneededifthesumisgreaterthan1001asweget
non-validBCDrepresentation.Theadditionofbinary6(0110)to
binarysumconvertsittothecorrectBCDrepresentationandalso
producesanoutputcarryasrequired(refertosection1-7)
•Thelogiccircuitthatdetectsthenecessarycorrectioncanbederived
fromthetableentries.Correction(addingdecimal6orbinary0110)is
neededwhenthebinarysumhasanoutput
K=1
Z
8Z
4=1
Z
8Z
2=1
6Fall 2022

7. Map Simplification of the Function C
1 1 1 1
1 1
1 1 1 1
d d d d
d d d d
d d d d
Z
8Z
4
00 01 11 10
00
01
11
10
k=0
Z
2Z
1
Z
8Z
4
00 01 11 10
00
01
11
10
k=1
C(K,Z
8,Z
4,Z
2,Z
1)= K+ Z
8Z
4+Z
8Z
2
Z
2Z
1
7Fall 2022

8. 8Fall 2022

9. Correction for BCD Adder
•Thisconditionforcorrectionandanoutputcarrycanbeexpressedas
C=K+Z
8Z
4+Z
8Z
2
•Infigure4-14,theoutputcarrygeneratedfromthebottomaddercan
beignoredsincethisisalreadyavailableattheoutputcarryterminal
•Adecimalparalleladderthataddsndecimaldigits(inBCDform)
needsnBCDadderstageswithoutputcarryfromonestage
connectedtotheinputcarryofnexthigher-orderstage
9Fall 2022

10. BCD Adder
Numbers that need
correction (add 6) are:
K Z
8Z
4Z
2Z
1
0 1 0 1 0 (10)
0 1 0 1 1 (11)
0 1 1 0 0 (12)
0 1 1 0 1 (13)
0 1 1 1 0 (14)
0 1 1 1 1 (15)
1 0 0 0 0 (16)
1 0 0 0 1 (17)
1 0 0 1 0 (18)
1 0 0 1 1 (19)
C = K + Z
8Z
4+Z
8Z
2
10Fall 2022

11. Binary Multiplier
•Multiplicationofthebinarynumberisperformedinthesamewayas
indecimalnumbers.Themultiplicandismultipliedbyeachbitofthe
multiplierstartingfromtheleastsignificantbit
•Eachsuchsuchmultiplicationformsapartialproduct.Successive
partialproductsareshiftedonepositiontotheleft.Thefinalproduct
isobtainedfromthesumofthepartialproducts
•Considerthebinarymultiplicationof2-bitnumberswhereB
1andB
2
aremultiplicandbitsandA
1andA
0aremultiplierbits.C
3C
2C
1C
0are
theproductbits
11Fall 2022

12. Binary Multiplier
•ThefirstpartialproductisformedbymultiplyingA
0byB
1B
0.The
multiplicationofanytwobitsproducesa1ifbothbitsare1,
otherwiseitproducesa0.ThisisidenticaltoANDoperation.
ThereforepartialproductcanbeimplementedwithanANDgatesas
showninfigure4-15
•ThesecondpartialproductisformedbymultiplyingA
1byB
1B
0and
shiftedonepositiontotheleft
•Thetwopartialproductsareaddedwithtwohalfadder(HA)circuits.
Iftherearemorebitsinthepartialproductsthenweusefulladders
toproducethesumofthepartialproducts
•Theleastsignificantbitofthepartialproductdoesn’thavetogo
throughanaddersinceitisformedbytheoutputofthefirstANDgate
12Fall 2022

13. 13Fall 2022

14. K-bit by J-bit Binary Multiplier
•Acombinationalcircuitforbinarymultiplierwithmorebitscanbe
constructedinasimilarway.AbitofthemultiplierisANDedwith
eachbitofthemultiplicandinasmanylevelsastherearebitsinthe
multiplier
•ThebinaryoutputineachlevelofANDgateisaddedwiththepartial
productofthepreviousleveltoformanewpartialproduct.Thelast
levelproducestheproduct
•ForJmultiplierbitsandKmultiplicandbitsweneed(JxK)AND
gatesand(J–1)Kbitadderstoproduceaproductof(J+K)bits
14Fall 2022

15. 4-bit by 3-bit binary multiplier
•Consideramultipliercircuitthatmultipliesabinarynumberoffour
bitsbyanumberofthreebits.
•LetthemultiplicandisrepresentedbyB
3B
2B
1B
0andthe
multiplierbyA
2A
1A
0
•SinceK=4andJ=3,weneed12ANDgatesandtwo4–bitadders
toproduceaproductofsevenbits
B
3B
2B
1B
0 Multiplicand
X A
2A
1A
0 Multiplier
0 A
0B
3A
0B
2A
0B
1A
0B
0Partial Product 0
A
1B
3A
1B
2A
1B
1A
1B
0 Partial Product 1
CoutS
3S
2 S
1 S
0
A
2B
3A
2B
2A
2B
1A
2B
0 Partial Product 2
C
6 C
5 C
4 C
3 C
2 C
1 C
0 Final Product
15Fall 2022

16. 16Fall 2022

17. The End
17Fall 2022