Lecutre-3 Design Methodology - Computer Architecture.pptx

Computer Architecture Design Methodology chapter presentation

1. Design Methodology Chapter-2 Computer Architecture and Organization- Jhon P. Hayes

2. Design Methodology System Design: A computer is an example of a system, which is defined informally as a collection – often a large and complex one – of objects called components, that are connected to form a consistent entity with a specific function or purpose. The function of the system is determined by the functions of its components and how the components are connected . If mathematical function f maps element a of A (input information items) onto element b of B (output information items), we write b = f (a) or b := f (a).

3. Design Methodology System Representation: A useful way of modeling a system is a graph or block diagram. Figure 2 shows a block diagram representing a small gate-level logic circuit called an EXCLUSIVE or modulo-2 adder . This circuit has the same general form as Figure 1 exhibiting a graph, which is a useful way of representing a system with the help of vertices and edges .

4. Design Methodology Structure versus behaviors : Structure of a system is the abstract graph consisting of its block diagram with no functional information . On the other hand, a behavioral description enables one to determine the corresponding output f(a) for any given input signal a to the system. Figure 3 shows one kind of behavioral description for the logic circuit of Figure 2 . This tabulation of all possible combinations of input-output values is called a truth table. Another description of the same Exclusive OR behavior can be written in terms of mathematical equations as follows, noting that f (a) = f(x 1 , x 2 ) f(0,0) = 0 f(0,1) = 1 f(1,0) = 1 f(1,1) = 0

5. Design Methodology (Structure versus behaviors) Figure 2.1: 1 2 3 4 5 6 7 8 Figure 1 : A graph with eight nodes and nine edges

6. Figure 2.2 NOT NOT AND AND OR x 1 x 2 x 1 x 2 + Figure 2 : A block diagram representing an Exclusive–OR logic circuit Input a Output x 1 x 2 f(a) 0 0 0 0 1 1 1 0 1 1 1 0 Design Methodology (Structure versus behaviors)

7. Input a Output x 1 x 2 f(a) 0 0 0 0 1 1 1 0 1 1 1 0 Figure 3: Truth table for the EXCLUSIVE-OR function Design Methodology (Structure versus behaviors)

8. Design Methodology Hardware description language: We can fully describe a system’s structure and behavior by means of a block diagram. The term schematic diagram is also used, in which it identify the functions of the components. We can convey the same detailed information by means of a hardware description language (HDL), a format that resembles a high-level programming language such as Ada or C.

9. Design Methodology VHDL Description of a Half Adder — entity half_adder is port ( x,y : in bit ; sum, carry : out bit ); end half_adder ; architecture behavior of half_adder is begin sum <= x xor y ; carry <= x and y ; end behavior Inputs Outputs x y sum carry 1 1 1 1 1 1 1 half_adder x y sum carry

10. Design Methodology Design Process: Given a system’s structure, the task of determining its function or behavior is termed analysis. The converse problem of determining a system structure that exhibits a given behavior is design or synthesis. Design Problem: Given a desired range of behavior and a set of available components, determine a structure(design) formed from these components that achieves the desired behavior with acceptable cost and performance.

11. Design Methodology The complexity of computer systems is such that the design problem must be broken down into smaller, easier tasks involving various classes of components. Each smaller part can be solved independently by different designers and each major design step can be implemented by iterative process as shown in Figure 4.

12. Begin End Construct an initial design Evaluate its cost and performance Are the design goals met? Modify the design to meet the goals Figure 4 Flowchart of an iterative design process Yes No

13. Design Methodology Design levels: The design of a computer is carried out at several levels of abstraction. Three such levels are The processor level , also called the architecture, behavior, or system level The register level , also called the register-transfer level (RTL ). The gate level , also called the logic level

14. Design Methodology The major computer design levels —

15. Gate level (logic) design is concerned with processing binary variables whose possible values are restricted to be the bits (binary digits) 0 and 1. The design components are logic gates, which are simple, memoryless processing elements and flip-flops which are bit-storage devices. Combinational logic: A combinational function also referred to as a logic or a Boolean function, is to mapping from the set of 2 n input combinations of n binary variables onto the output values 0 and 1. The Gate Level

16. Common Logic Gates Fig 5: C ommon Boolean logic gates with symbols and truth tables

17. Figure 2.9 shows the truth table for a pair of three variable functions, s (x , y , c -1 ) and c (x , y , c -1 ), which are the sum and carry output, respectively, of a logic circuit called a full adder . This useful logic circuit computes the numerical sum of its three input bits using binary(base 2) arithmetic: c s = x plus y plus c -1 For example, the last row of the truth table of Figure 2.9(a) express the fact that the sum of three 1s is c s = 11 2 that is the base-2 representation of the number three (3). The Gate Level

18. The Gate Level

19. Two alternative gate level design for the full adder appear in Figure 2.9 c and 2.9 d . The AND-OR circuit of Figure 2.9 c is defined by logic equations— s = x y c -1 + x y c -1 + x y c -1 + x y c -1 -------- (1) Equation (1) represents sum-of-products (SOP) . c = (x + c -1 )(x + y )(y + c -1 ) -------- (2) Equation (2) represents product-of-sum (POS) . The Gate Level

20. The circuit of Figure 2.9c is called a two-level or depth-two logic circuit. This is because there are only two gates along each path: one AND and one OR. These gates connect the adder’s primary inputs x , y ​, and c -1 ​ to its primary outputs s and​ c . This assumes that each primary input variable is available in both true and complemented (inverted) forms . The number of logic levels is defined by the number of logic gates along the circuit’s longest IO path. The Gate Level

21. Each gate imposes some delay on every signal that propagates through it . The typical delay per gate is approximately 1 nanosecond (ns ). That’s why the fewer the logic gates, the faster the circuit . The half-adder-based circuit in Figure 2.9 b has input-output (IO) paths containing up to four gates, making it a four-level logic design. The two-level adder in Figure 2.9 c is twice as fast as the four-level design due to fewer logic levels . The Gate Level

22. However , the two-level adder uses more gates, resulting in higher hardware costs . A key task in logic design is synthesizing a circuit that balances hardware cost (number of gates) with operating speed (number of logic levels). The Gate Level

23. By adding memory to a combinational circuit in the form of 1-bit storage elements called flip-flops, we obtain a sequential circuit. Flip-flops rely on an external clock signal CLK to synchronize the time at which they respond to change on their data lines. They are also designed to be unaffected by transient signal changes ( noise) produced by the combinational logic that feeds them. Fig 7 : Flip-flops Flip-flops

24. Four bit ripple carry : a ) logic structure b ) high level symbol Flip-flops 4-bit Adder A B Carry in C Carry out C 4 Sum S

25. A sequential circuit consists of a combinational circuit and a set of flip-flops. The combinational logic forms the computational or data processing part of the circuit. The flip-flops store information about the circuit’s past behavior; T his stored information defines the circuit’s internal state. (output depends on present input and past input) Sequential Circuits

26. The behavior of a sequential circuit can be specified by a state table that includes the possible values of its primary outputs and its internal states. Fig 2.12a shows the state table of a small but useful sequential circuit, a serial adder. Because the serial adder has only two internal states, its memory consists of a single flip-flop. Internal state S means that the previous carry signal c(i - 1) = 0 and S 1 means that c(i - 1) = 1. Sequential Circuits

27. Sequential Circuits

28. At the register or register-transfer level , related information bits are grouped into ordered sets called words or vectors . The primitive (Modern) components are small combinational or sequential circuits intended to process or store words. The Register Level

29. Register level Components: Type Component Functions Combinational Word Gates Logical (Boolean) Operation Multiplexers Data routing; general, combinational function Decoder, encoder Code checking and conversion Adders Addition and subtraction Arithmetic Logic Unit Numerical and logical operations Programmable logic devices General sequential functions. Sequential (Parallel) registers, Shift registers Information storage; serial-parallel conversion Counter, Programmable logic devices Control/timing signal generation, General sequential functions. The Register Level

30. General block representation of a Register- level Component: Components are commonly represented in the circuit by blocks. The block is associated with a number of signal lines representing something that is involved in the working of the block. Single signal lines may represent multiple bits in parallel ( e.g., n > 1 shown as /n). The Register Level

31. General block representation of a Register- level Component: Signal lines are separated into data and control lines The control line indicates the type of operation to be performed by the line when the line is in its active or asserted state . Control lines fall into: Select Lines : Choose among several operations. Enable Lines : Indicate conditions or timing for operations. The data lines are essentially I/O lines attached to the unit in the form of - Input Lines : Feed data for operations . Output Lines : Provide results of operations . The Register Level

32. Register-Level Design: A register-level system consists of a set of registers linked by combinational data transfer and data processing circuits. A block diagram can define its structure and the set of operations it performs on data words can define its behavior. The Register Level

33. Register-Level Design: The Register Level

34. Register-Level Design: A simple register-level system, shown in Fig 2.38a , performs a single action, in this case, the add operation Z = A + B . Fig 2.38b shows a more complicated system that can perform several different operations. Such a multifunction system is generally partitioned into a data-processing part called a datapath and a controlling part, the control unit , responsible for selecting and controlling the actions of the datapath. In Fig .38b, CU selects the operation (add, shift, and so on) for the ALU to perform in each clock cycle. The Register Level

35. Design Techniques: The design problem for register-level systems is as follows: “Given a set of operations to be executed, design a circuit using a specified set of register-level components that implement the desired functions while satisfying certain cost and performance criteria.” The Register Level

36. General Approach to the Design Problem — Define Behavior: Specify the desired behavior as a sequence of register-transfer operations. Ensure each operation aligns with available design components, forming an algorithm (AL). Analyze Components: Determine the types and quantities of components required for the datapath (DP). The Register Level

37. Construct Datapath (DP): Create a block diagram for DP using identified components. Ensure all data paths implied by AL are present while meeting performance and cost constraints. Add Control Signals: Identify control signals needed for DP operations. Integrate logic or control points into DP to manage these signals. Design Control Unit (CU): Develop CU to generate and manage the control signals as required by AL. Verify Design: Simulate the design to confirm correctness and compliance with performance and cost goals. The Register Level

38. The Processor level There are four main groups of processor level components: - Processors - Memories - IO devices - Interconnection networks

39. System bus Cache Program Counter PC Instruction register IR Address generation Instruction decoding Arithmetic logic unit Register file Main memory and IO system Program control Unit (I - unit) Control signals Datapath E - unit Figure 10: Internal organization of a CPU and cache memory

40. The Processor level Figure 10 shows the essential internal organization of a CPU at the register level. The CPU contains the logic needed to execute its particular instruction set and is divided into datapath and control unit. The control part ( I - unit ) generates the address of instructions and data stored in external memory. In this particular system a cache memory is interposed between the main memory M and the CPU. Each memory request generated by the CPU is first directed to the cache.

41. The Processor level If the required information is not currently assigned to the cache, the request is redirected to M and cache is automatically updated from M. The I – unit fetches instructions from the cache or M and decodes them to derive the control signals needed for their execution. The CPU’s datapath ( E - unit ) has the arithmetic – logic circuits that execute most instructions; it has also a set of registers for temporary data storage. The CPU manages a system bus , which is the main communication link among the CPU cache subsystem, main memory and the I/O devices.

42. The Processor level In one clock cycle the CPU can perform a register-transfer operation, such as fetching an instruction word from M via the system bus and loading it into the instruction register IR. This operation can be expressed formally by IR:= M(PC); Where PC is the program counter used by the CPU to hold the expected address of the next instruction word. Once in the I-unit, an instruction is decoded to determine the actions needed for its execution. The entire process of fetching, decoding and executing an instruction constitutes the CPU’s instruction cycle .

43. The Processor level Memories: The memory part of a computer can be divided into several major subsystem. - Main memory M, consisting of relatively fast storage ICs connected directly to, and controlled by, the CPU. - Secondary memory, Consist of less expensive devices that have very high storage capacity. These devices often involve mechanical motion and so are much slower than M. They are generally connected indirectly (via M) to the CPU and form part of the computer’s I/O system. - Other memory, many computer have a third type of memory called a cache, which is positioned between the CPU and main memory. Some or all of cache may be integrated on the same IC chip as the CPU itself.

44. The Processor Level ( Cache memory ) Main Memory Processor Cache Processor Block Transfer Word Transfer Cache memory is a small amount of fast but expensive memory placed between the processor and main memory (512 KByte on the P-III processor). In some PCs there may be extra cache attached directly to the motherboard. When the processor attempts to read a word of main memory, a check is made first to determine if the word is in the cache. If it is, a copy of the word is transferred to the processor. If not, a block of main memory, consisting of a fixed number of words, is transferred into the cache and then a copy of the required work is transferred to the processor. There are two types of cache memory: External cache memory, Internal cache memory Fig 11: Processor Cache Memory

45. The Processor level I/O devices: Input-output devices are the means by which a computer communicates with the outside world. A primary function of I/O devices is to act as data transducers. I/O devices do not alter the information content or meaning of the data on which they act. Since data is transferred and processed within a computer system in the form of digital electrical signals, input (output) devices transform other forms of information to (from) digital electrical signal.

46. The Processor level Interconnection networks: Processor level components communicate by word-oriented buses. In systems with many components, communication may be controlled by a subsystem called an interconnection network ; terms such as switching network , communications controller , and bus controller are also used in this context. Internal Communication: The System BUS: A bus is a set of parallel wires connecting two or more components of the computer. The number of lines is referred to as the width of the bus. Bus lines are classified into three functional groups: Control Bus Data Bus Address Bus

47. The Processor Level ( System Bus ) Fig 12: System Bus

48. The Processor Level (Internal Communication ) Interrupts: An interrupt is a signal from some device/ source seeking the attention of the processor. Types of Interrupts Program Timer Input / Output Hardware failure