LOGIC LEVEL PPT.pptx on low power vlsi design

ppt on low power vlsi on logic level techniques

1. PRESENTATION LOW POWER VLSI DESIGN Logic Level Techniques Presented By MUSKAN.S

2. CONTENTS Gate Reorganization Signal Gating Logic Encoding State machine Encoding Precomputation Logic 2

3. Logic Design Logic design was once the primary abstraction level where automatic design synthesis begins The most prevalent theme in logic level power optimization techniques is the reduction of switching activities Switching activities directly contribute to the charging and discharging capacitance and the short circuit power Some switching activities are the result of unspecified or undefined behavior of a logic system that are not related to its power operation Such stray switching activities should be eliminated or reduced if possible However, suppressing unnecessary activities usually requires additional hardware logic that increases the area and consumes power

4. Gate Reorganization G ate reorga n i zat i on i s a p p l i ed t o g a t e le v el n e t w ork t o pr educe logically equivalent networks with different qualities for power, area, and delay. T he comp le x i t y of t he g a t e reorg a n i zation pro b lem l i m its man u al so l uti o n to small circuits only. Gate level reorganization is a central operation of logic synthesis. Most g ate re o rg a n i zati o n tasks are p e rformed b y a u tomated sof t w are i n the logic synthesis system

5. Local Restructuring Gate reorganization is an operation to transform one logic circuit to another that is functionally equivalent L o g ic restructur i ng tech n i q u es use l oc a l res t ruc t uring ru l es t o transform one network to another Some basic transformation operators are: Combine several gates into a single gate Decompose a single gate into several gates Duplicate a gate and redistribute its output connections Delete a wire Add a wire Eliminate unconnected gates

6. Local transformation Operators for gate reorganization Local Restructuring Fig1. Local transformation operators for gate reorganization

7. Local transformation Operators for gate reorganization Local Restructuring Fig2. Local transformation operators for gate reorganization

8. Local Restructuring COMBINE operator can be used to hide high frequency nodes inside a cell so that the node capacitance is not being switched DECOMPOSE and DUPLICATE operators help to separate the critical path from the non critical ones so that the latter can be sized down DELETE WIRE operator reduces the circuit size ADD WIRE operator helps to provide an intermediate circuit that may eventually lead to a better one

9. Signal Gating Signal gating refers to a class of general techniques to mask unwanted switching activities from propagating forward, causing unnecessary power dissipation The probabilistic techniques are often used for switching activity analysis The simplest method to implement signal gating is to put an AND/OR gate at the signal path to stop the propagation of the signal when it needs to be masked Another method is to use a latch or flip flop to block the propagation of the signal Sometimes a transmission gate or tristate buffer can be used in place of a latch if charge leakage is not a concern The various logic implementation of signal gating is shown below

10. Signal Gating Fig3. Various logic signal implementation of signal gating The signals at the bottom of the circuits are control signals used to suppress the source signal on the left from propagating to the gated signal on the right Control signal frequency must be low

11. Logic Encoding The logic designer of a digital circuit often has the freedom of choosing a different encoding scheme as long as the functional specification of the circuit is met For e.g. an 8 bit counter can be implemented using the binary counting sequence or the gray code sequence Different encoding implementation often lead to different power, area and delay tradeoff The encoding techniques require the knowledge of signal statistics in order to make design decisions

12. Binary versus Gray Code Counting Consider two n-bit counters implemented with Binary and Gray code counting sequences The counting sequences of the two counters are shown in Table1 Toggle activities of Binary versus Gray counter are shown in Table2 T abl e 1 T abl e 2

13. Binary versus Gray Code Counting When n is large, the Binary counter has twice as many transitions as the Gray counter Since the power dissipation is related to toggle activities, a Gray counter is generally more power efficient than a Binary counter

14. Bus Invert Encoding Bus invert encoding is a low power encoding technique that is suitable for a set of parallel synchronous signals e.g.: off-chip busses At each clock cycle, the data sender examines the current and next values of the bus and decides whether sending the true or the compliment signal leads to fewer toggles Since the data signals on the bus may be complemented, an additional polarity signals is sent to the bus receiver to decode the bus data properly

15. Bus Invert Encoding Example Example: Eight bit bus 00001100 → 10001101 has Two transitions. 00001100 → 1 000110 1 (D H =2) Polarity Bit =0 10001101 → 01110001 10001101 → 011100 01 (D H =6) Polarity Bit =1 Now bits of second pattern are inverted, then instead 01110001 → 10001110 Tx 10001110 will have only TWO transition

16. Bus Invert Encoding Encode N-bit string using N+1bits. Compute hamming Distance D H D H >N/2: Set Polarity Bit=1 ( Invert Next data valve) otherwise Polarity bit=0 (Next data value) Fig4. Architecture of bus invert encoding

17. Bus Invert Encoding The maximum number of toggeling bits of the inverted bus is reduced from n to n/2 The assertion of the polarity signal tells the receiver to invert the received bus signals

18. Bus Invert Encoding We assume that each bit of the bus has the uniform random probability distribution and is uncorrelated in time. This means that the current value of the bus is independent of its previous values and all bits are mutually uncorrelated. The probability of a k-bit transition on an n-bit regular bus is 𝑃𝑘 = 1 2 𝑛 𝑛 ! 𝑛−𝑘 !𝑘! The expected number of transitions E [P] of the regular bus is thus

19. Bus Invert Encoding In the bus invert scheme, additional one polarity bit to the bus. For the (n + I)-bit inverted bus, the number of bit transitions at any given clock cycle is never more than n/2. At each clock cycle, if there is a k-bit transition on the inverted bus, one of the following two conditions must occur: The polarity bit does not toggle: the probability of this condition is identical to that of a k-bit transition on a regular bus P k . The polarity bit toggles: this means that there are k - 1 bit transitions in the inverted bus, which implies that there are n - k + 1 bit transitions in the corresponding regular bus. This probability is given by P (n - k + 1) · 𝑃 1 𝑛! ( 𝑛 − 𝑘 + 1 ) = 2 𝑛 𝑛−𝑛+𝑘−1 !(𝑛−𝑘+1)! ) = 1 2 𝑛 𝑛 ! 𝑘−1 !(𝑛−𝑘+1)! =P ( k - 1)

20. Bus Invert Encoding Thus, the probability of a k-bit transition on the (n + I) -bit inverted bus is The expected number of transitions E [Q] on an inverted bus is thus

21. Bus Invert Encoding Table3. Efficiency of bus invert encoding under uniform random signal The design decision to apply bus invert technique is dependent on signal statistics and the overhead associated with the polarity decision logic, the polarity signal and the invert/pass gates.

22. State Machine Encoding A state machine is an abstract computation model that can be readily implemented using Boolean logic and flip flops In logic synthesis environment, a state transition graph is specified by the designer and the synthesis system will produce a gate level circuit based on the machines specification The state transition graph is a functional description of a machine specifying the inputs and outputs of the machine under a particular state and its transition to the next state Fig5. Hardware architecture of synchronous machine

23. State Machine Encoding The very first step of a state machine synthesis process is to allocate the state register and assign binary codes to represent the symbolic states. This process is called the encoding of a state machine The encoding of a state machine is one of the most important factors that determine the quality (area, power, speed etc) of the gate level circuit Transition Analysis of State Encoding T he k e y p a rame t er t o t he p o w er e f f ic i e n c y of s t ate e n cod i ng i s t he expected number of bit transitions E[M] in the state register Another parameter is the expected number of transitions of output signals

24. State Machine Encoding The very first step of a state machine synthesis process is to allocate the state register and assign binary codes to represent the symbolic states. This process is called the encoding of a state machine  The encoding of a state machine is one of the most important factors that determine the quality (area, power, speed etc ) of the gate level circuit  Transition Analysis of State Encoding  The key parameter to the power efficiency of state encoding is the expected number of bit transitions E[M] in the state register  Another parameter is the expected number of transitions of output signals

25. State Machine Encoding Fig6. Functionally identical machines with different encoding

26. State Machine Encoding The expected number of state bit transitions E[M] is given by the sum of products of edge probabilities and their associated number of bit flips as dictated by the encoding However, a state encoding with the lowest E[M] may not be the one that results in the lowest overall power dissipation The reason is that the particular encoding may require more gates in the combinational logic, resulting in more signal transitions and power The synthesized area and power dissipation of some randomly encoded state machines is shown below

27. State Machine Encoding Fig7. Effect of state encoding on synthesized area and power dissipation

28. Clock-Gating in Moore FSM 29

29. Precomputation Logic Prec o mp uta t i on l o g i c o p timi zati o n i s a meth o d t o tra d e ar e a for p o w er i n a synchronous digital circuit The principle of precomputation logic is to identify logical conditions at some inputs to a combinational logic that is invariant to the output Since those input values do not affect the output, the input transitions can be disabled to reduce switching activities One variant of precomputation logic is shown below Let R1 and R2 are registers with a common clock feeding a combinational logic circuit with a known Boolean function f(x) D u e t o t he n a t ure of t he f u n c t io n f ( x ), t h e re m a y be some con d iti o ns under which the output of f(x) is independent of the logic value of R2

30. Fig8. A variant of precomputation logic Precomputation Logic

31. Precomputation Logic Under such conditions, we can disable the register loading of R2 to avoid causing unnecessary switching activities, thus conserving power The Boolean function f(x) is correctly computed because it receives all required values from R1 To generate the load disable signal to R2, a precomputation Boolean function g(x) is required to detect the condition at which f(x) is independent of R2 g(x) depends on the input signals of R1 only because the load disable condition is independent t of R2, otherwise f(x) will depend on the inputs of R2 when the load disable signal is active Assuming uncorrelated input bits with uniform random probabilities where every bit has an equal probability of or 1

32. Precomputation Logic There is 50% probability that An Å Bn = 1 and the register R2 is disabled in 50% of the clock cycles Therefore, with only one additional 2 input XOR gate, we have reduced the signal switching activities of the 2n-2 least significant bits at R2 to half of its original expected switching frequency Fig9. Binary comparator function using precomputation logic

33. Precomputation Logic Also, when the load disable signal is asserted, the combinational logic of the comparator has fewer switching activities because the outputs of R2 are not switched The extra power required to compute An Å Bn is negligible compared to the power saving even for moderate size of n

34. Precomputation Logic Prior knowledge of the input signal statistics to apply the precomputation logic technique. In comparator design, if the probability of An  Bn is close to zero, the precomputation logic circuit may be inferior, in power and area, compared to direct implementation. Experimental results [5.16] have shown up to 75% power reduction with an average of 3% area overhead and 1 to 5 additional gate-delay in the worst-case delay path.

35. Precomputation Condition Given f(X), R I and R 2 , there is a systematic method to derive a precomputation function g(X). Let f(p 1 , p 2, p 3, p 4, ... , p m, x 1 , x 2 , x 3 , ... , x n) be the Boolean function Where p 1 ...p m the precomputed inputs corresponding to R I x 1 ,...x n are the gated inputs corresponding to R2. Let fx i be the Boolean function obtained by substituting X i = 1

36. Precomputation Logic

37. Precomputation Logic

38. Al t ernate P r e c om p ut a tion L o gic The precomputation scheme based on Shannon's decomposition is states that a Boolean function f(x1,…,xn) can be decomposed with respect to the variable xi as follows: The equation allows us to use xi as the load disable signal

39. Precomputation Logic When xi= (xi= 1)the inputs to the logic block fxi can be disabled T he mu l t iple x er s e lects t he o u t p u t of t he comb in a t io n a l lo g ic b l ock active t h a t is This means that only one combinational logic block is activated at any clock cycle P o w er sa v in g i s s a v in g i s ach i e v ed i f e a ch of t he t w o d e comp o s e d lo g ic blocks consumes less power than a direct implementation However, the precomputation architecture consumes more area and delay in general The latch based precomputation architecture is shown below

40. Precomputation Logic Fig10. A precomputation architecture based on Shannon's decomposition This architecture is also called guarded evaluation because some inputs to the logic block C2 are isolated when the signals are not required, to avoid unnecessary transition

41. Precomputation Logic Fig11. A latch-based precomputation architecture Transmission gates may be used in place of the latches if the charge storage and noise immunity conditions permit

42. Design issues in Precomputation Logic Techniques The basic design steps with precomputation logic are as follows: Select precomputation architecture Determine the precomputed inputs R1 and gated inputs R2 given the function f(x) With R1 and R2 selected, find a precomputation logic function g(x) Note that g(x) is not unique and the choice greatly affects the power efficiency . The function g(x) may also fail to exist for poor choices of R1 and R2 Evaluate the probability of precomputation condition and the potential power savings. Make sure that the final circuit is not overwhelmed by the additional logic circuitry and power consumption required to compute g(x)

43. Design issues in Precomputation Logic Techniques After R1, R2 and g(x) are determined, the precomputation logic can be s y n t he s i z e d u s i n g a logi c sy n t he s i s t oo l Precomputation by definition is creating redundant logic The logic circuit that performs precomputation generally pose difficulties in testing

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