memory Organization in computer organization

memory oranization

1. Sunday, April 21, 2024 MEMORY ORGANIZATION

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3. Sunday, April 21, 2024 Memory Hierarchy Main Memory Auxiliary Memory Associative Memory Cache Memory Virtual Memory MEMORY ORGANIZATION

4. Sunday, April 21, 2024 Register Cache Main Memory Magnetic Disk Magnetic Tape Storage capacity------  Access Time --------  MEMORY ORGANIZATION Computer System Memory Hierarchy

5. Sunday, April 21, 2024 Magnetic tapes Magnetic disks I/O processor CPU Main memory Cache memory Auxiliary memory Memory Hierarchy is to obtain highest possible access speed while minimizing the total cost of the memory system MEMORY ORGANIZATION Components In Memory Hierarchy

6. Sunday, April 21, 2024 MAIN MEMORY RAM and ROM Chips RAM chip Block Diagram ROM chip Block Diagram Chip select 1 Chip select 2 Read Write 7-bit address CS1 CS2 RD WR AD 7 128 x 8 RAM 8-bit data bus CS1 CS2 RD WR 0 0 x x 0 1 x x 1 0 0 0 1 0 0 1 1 0 1 x 1 1 x x Memory function Inhibit Inhibit Inhibit Write Read Inhibit State of data bus High-impedence High-impedence High-impedence Input data to RAM Output data from RAM High-impedence Chip select 1 Chip select 2 9-bit address CS1 CS2 AD 9 512 x 8 ROM 8-bit data bus Function Table

7. Sunday, April 21, 2024 MEMORY ADDRESS MAP RAM 1 RAM 2 RAM 3 RAM 4 ROM 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF 0200 - 03FF Component Hexa address 0 0 0 x x x x x x x 0 0 1 x x x x x x x 0 1 0 x x x x x x x 0 1 1 x x x x x x x 1 x x x x x x x x x 10 9 8 7 6 5 4 3 2 1 Address bus Memory Connection to CPU - RAM and ROM chips are connected to a CPU through the data and address buses - The low-order lines in the address bus select the byte within the chips and other lines in the address bus select a particular chip through its chip select inputs Address space assignment to each memory chip Example: 512 bytes RAM and 512 bytes ROM

8. Sunday, April 21, 2024 CS1 CS2 RD WR AD7 128 x 8 RAM 1 CS1 CS2 RD WR AD7 128 x 8 RAM 2 CS1 CS2 RD WR AD7 128 x 8 RAM 3 CS1 CS2 RD WR AD7 128 x 8 RAM 4 Decoder 3 2 1 WR RD 9 8 7-1 10 16-11 Address bus Data bus CPU CS1 CS2 512 x 8 ROM AD9 1- 7 9 8 Data Data Data Data Data CONNECTION OF MEMORY TO CPU

9. Sunday, April 21, 2024 CONNECTION OF MEMORY TO CPU

10. Sunday, April 21, 2024 Memory Address Mapping Table To CPU

11. Sunday, April 21, 2024 Auxiliary Memory Magnetic Disks Magnetic Tape

12. Sunday, April 21, 2024 Auxiliary Memory

13. Sunday, April 21, 2024 Auxiliary Memory Magnetic Disks

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15. Sunday, April 21, 2024 Auxiliary Memory Magnetic Tape

16. Sunday, April 21, 2024 Auxiliary Memory Magnetic Tape

17. Associative Memory Content Addressable Memory (CAM). Sunday, April 21, 2024

18. Sunday, April 21, 2024 Searching objects in memory. Data-processing applications require the search of items in a table stored in memory. Assembler program searches the symbol address table to extract the symbol's binary equivalent. An account number may be searched in a file to determine the holder's name and account status. The way to search a table is to store all items where they can be addressed in sequence. Searching Strategy for choosing a sequence of addresses, reading the content of memory at each address, and comparing the information read with the item being searched until a match occurs. The number of accesses to memory depends on the location of the item and the efficiency of the search algorithm. Search algorithms have been developed to minimize the number of accesses while searching for an item in a random or sequential access memory

19. Sunday, April 21, 2024 If stored data identified by the content of the data itself - The time required to find an item in memory can be reduced . Associative Memory or Content Addressable Memory (CAM). - Accessed simultaneously and in parallel by data content rather than address. Write Operation : No address is given When a word is written in an associative memory, the memory is capable of finding an empty unused location to store the word. Read Operation : The content of the word, or part of the word, is specified. When a word is to be read from an associative memory The memory locates all words which match the specified content and marks them for reading

20. Sunday, April 21, 2024 Hardware Organization

21. Sunday, April 21, 2024 Three leftmost bits of A are compared with memory words because K has 1's in these positions. Bit configuration of Argument register (A) Key register (K)

22. Sunday, April 21, 2024 Associative memory of m word, n cells per word

23. Sunday, April 21, 2024 One cell of associative memory.

24. Sunday, April 21, 2024 Match Logic Boolean function AND operation of all n terms. We need m such functions, one for each word i = 1, 2, 3, ... , m.

25. Sunday, April 21, 2024 Match logic for one word of associative memory.

26. Sunday, April 21, 2024 Read Operation Write Operation Operations on Associative Memory

27. Sunday, April 21, 2024 Cache Memory

28. Sunday, April 21, 2024 Locality Of Reference : R eferences to memory at given interval of time is confined within few localized areas in memory.

29. Sunday, April 21, 2024 Magnetic tapes Magnetic disks I/O processor CPU Main memory Cache memory Auxiliary memory Memory Hierarchy is to obtain highest possible access speed while minimizing the total cost of the memory system MEMORY ORGANIZATION Components In Memory Hierarchy

30. Sunday, April 21, 2024 Cache Memory Example

31. Sunday, April 21, 2024 The basic characteristic of cache memory is its fast access time. The transformation of data from main memory to cache memory is done by mapping process.

32. Sunday, April 21, 2024 Hit Ratio: The performance of cache memory measured in terms of quantity hit ratio. The ratio of the number of hits divided by the total CPU references (hits + misses) to memory. Hit : the CPU finds the word in the cache Miss : the word is not found in cache (CPU must read main memory) Performance Of Cache Memory

33. Sunday, April 21, 2024 Cache memory access time = 100 ns main memory access time = 1000 ns and hit ratio = 0.9

34. Sunday, April 21, 2024 Cache memory mapping techniques Associative mapping Direct mapping Set associative mapping

35. Sunday, April 21, 2024 The fastest and most flexible cache organization uses an associative memory Associative mapping The associative memory stores both the address and content (data) of the memory word. Any location in cache to store any word. - any location in cache to store any word from main memory .

36. Sunday, April 21, 2024 Associative mapping

37. Sunday, April 21, 2024 How Cache Memory Works Cache read operation

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39. Sunday, April 21, 2024 Cache write operation How Cache Memory Works

40. Sunday, April 21, 2024 Example for ( i =0; i <M; i ++) s = s + i ;

41. Sunday, April 21, 2024 Example for ( i =0; i <M; i ++) for(j=0; j<N; j++) X[ i ][j] = X[ i ][j] + K; Each element of X is double (eight bytes) Loop is executed (M * N) times Placing the code in cache avoids access to main memory Repetitive use (one of the factors) Temporal locality Prefetching data Spatial locality

42. Sunday, April 21, 2024 Direct mapping

43. Sunday, April 21, 2024 Direct Mapping Cache Organization

44. Sunday, April 21, 2024 Hit ratio drop if two or more words whose addresses have the same index but different tags are accessed repeatedly.

45. Sunday, April 21, 2024 Direct mapping cache with block size of 8 words

46. Sunday, April 21, 2024 Set-Associative Mapping Two way set .. associative mapping cache

47. Sunday, April 21, 2024 Virtual Memory

48. Sunday, April 21, 2024 In a memory hierarchy programs and data are first stored in auxiliary memory. Portions of a program or data are brought into main memory as they are needed by the CPU

49. Sunday, April 21, 2024 Virtual memory permit to construct programs as though a large memory space were available, equal to the totality of auxiliary memory. Each address that is referenced by the CPU goes through an address mapping from virtual address to a physical address in main memory Virtual memory provides a mechanism for translating programgenerated addresses into correct main memory locations. This is done dynamically, while programs are being executed in the CPU. The translation is handled automatically by the hardware by a mapping table.

50. Sunday, April 21, 2024 Address Space and Memory Space An address used by a programmer will be called a virtual address. The set of such addresses the address space. The set of addresses generated by programs as they reference instructions and data An address in main memory is called a location or physical address. The set of such locations is called the memory space. It consists actual main memory locations directly addressable for processing . The address and memory spaces are identical. The address space is allowed to be larger than the memory space in computers with virtual memory.

51. Sunday, April 21, 2024 Example for 1024k auxiliary memory and 32k main memory Address space =1024k Virtual address bits =20 Memory space = 32k Physical address bits =15 Programs and data are transferred to and from auxiliary memory and main memory based on demands imposed by the CPU

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53. Sunday, April 21, 2024 Mapping function Between virtual address space and physical address space

54. Sunday, April 21, 2024 Address Mapping Using Pages The table implementation of the address mapping is simplified if the information in the address space and the memory space are each divided into groups of fixed size. The physical memory is broken down into groups of equal size called blocks, range from 64 to 4096 words each. The term page refers to groups of address space of the same size.

55. Sunday, April 21, 2024 Splitting Address Space into Pages The mapping of virtual address is considered to be represented by two numbers: Page number address Line (word) within the page.

56. Sunday, April 21, 2024 Memory mapping table in a paged system 8K x 12 auxiliary memory and 4K x 12 main memory with block size = page size = 1k

57. Sunday, April 21, 2024 Memory mapping table in a paged system 8K x 12 auxiliary memory and 4K x 12 main memory with block size = page size = 1k

58. Sunday, April 21, 2024 Associative Memory Page Table

59. Sunday, April 21, 2024 Page fault and Replacement Replacement algorithms FIFO (First-In First-Out): Select the item has been in the Cache the longest. LRU (Least Recently Used): Select the item that has been least recent used by CPU Random Replacement: Select the item randomly.

60. Sunday, April 21, 2024 Any Queries?

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