S. B. PATIL COLLEGE OF ENGINEERING , INDAPUR,DIST:PUNE. Prof.P.U.Chavan Assistant Professor Department of Computer Engineering
Microprocessor (2019 Course) INSEM 30 MARKS Unit 1.80386DX- Basic Programming Model and Applications Instruction Set Unit 2.Systems Architecture and Memory Management ENDSEM 70 MARKS Unit 3.Protection and Multitasking Unit 4.Input-Output , Exceptions and Interrupts Unit 5.Initialization of 80386DX, Debugging and Virtual 8086 Mode Unit 6. 80387 Coprocessor and Introduction to Microcontrollers
Unit 1.80386DX- Basic Programming Model and Applications Instruction Set Memory Organization and Segmentation- Global Descriptor Table, Local Descriptor Table, Interrupt Descriptor Table, Data Types, Registers, Instruction Format, Operand Selection, Interrupts and Exceptions Applications Instruction Set- Data Movement Instructions, Binary Arithmetic Instructions, Decimal Arithmetic Instructions, Logical Instructions, Control Transfer Instructions, String and Character Transfer Instructions, Instructions for Block Structured Language, Flag Control Instructions, Coprocessor Interface Instructions, Segment Register Instructions, Miscellaneous Instructions.
Global Descriptor Table:- GDT is Global Descriptor Table.GDT represent global memory area shared by all tasks. Size of GDT is 64KBytes. 48 bit GDTR register is used to track GDT memory. Out of this 48bit ,32bit is base address and 16bit Limit. GDTR register selects any descriptor from GDT.
Local Descriptor Table:- LDT represents local memory area shared by different tasks. LDT is not defined as independent table. LDT Descriptor is defined inside GDT. LDTR provide index of LDT Descriptor into GDT. It Changes as task Changes. It is not like GDT.
Unit 2.Systems Architecture and Memory Management Systems Architecture- Systems Registers, Systems Instructions. Memory Management- Segment Translation, Page Translation, Combining Segment and Page Translation.
Unit 3.Protection and Multitasking Protection - Need of Protection, Overview of 80386DX Protection Mechanisms, Segment Level Protection, Page Level Protection, Combining Segment and Page Level Protection. Multitasking - Task State Segment, TSS Descriptor, Task Register, Task Gate Descriptor, Task Switching, Task Linking, Task Address Space.
Protection Mechanism The protection hardware of the 80386 is an integral part of the memory management hardware. Protection applies both to segment translation and to page translation. User can not currupt file in interface .
Unit 4.Input-Output, Exceptions and Interrupts Input-Output- I/O Addressing, I/O Instructions, Protection and I/O Exceptions and Interrupts- Identifying Interrupts, Enabling and Disabling Interrupts, Priority among Simultaneous Interrupts and Exceptions, Interrupt Descriptor Table (IDT), IDT Descriptors, Interrupt Tasks and Interrupt Procedures, Error Code, and Exception Conditions.
Unit 5.Initialization of 80386DX, Debugging and Virtual 8086 Mode Initialization- Processor State after Reset, Software Initialization for Real Address Mode, Switching to Protected Mode, Software Initialization for Protected Mode, Initialization Example, TLB Testing Debugging- Debugging Features of the Architecture, Debug Registers, Debug Exceptions, Breakpoint Exception Virtual 8086 Mode- Executing 8086 Code, Structure of V86 Stack, Entering and Leaving Virtual 8086 Mode.
Unit 6.80387 Coprocessor and Introduction to Microcontrollers 80387 NDP- Control Register bits for Coprocessor support, 80387 Register Stack, Data Types, Load and Store Instructions, Trigonometric and Transcendental Instructions, Interfacing signals of 80386DX with 80387. Introduction to Microcontrollers: Architecture of typical Microcontroller, Difference between Microprocessor and Microcontroller, Characteristics of 8 bit and 16 bit microcontrollers, Application of Microcontrollers