Module 1 of VLSI Design and Testing.pptx

VTU VLSI DESIGN AND TESTING

1. Module 1: Introduction and MOS Theory HKBK, Sufia Banu

2. Outline Introduction: A Brief History MOS Transistors CMOS Logic Pass Transistors CMOS Latches & Flip-Flops MOS Transistor Theory: Introduction Long Channel I-V Characteristics Non-ideal I-V Effects DC Transfer Characteristics

3. A Brief History 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 2010 Intel Core i7 m processor 2.3 billion transistors 64 Gb Flash memory > 16 billion transistors Courtesy Texas Instruments [Trinh09] © 2009 IEEE

4. Growth Rate 53% compound annual growth rate over 50 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society [Moore65] Electronics Magazine

5. Annual Sales >10 19 transistors manufactured in 2008 1 billion for every human on the planet

6. Invention of the Transistor Vacuum tubes ruled in first half of 20 th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs See Crystal Fire by Riordan, Hoddeson AT&T Archives. Reprinted with permission.

7. Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration

8. Having only Pmos Txs suffered from poor performance, yield and reliability. In 1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power MOS Integrated Circuits Intel 1101 256-bit SRAM Intel 4004 4-bit m Proc [Vadasz69] © 1969 IEEE. Intel Museum. Reprinted with permission.

9. Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Integration Levels SSI : 10 gates(7404 inverter) MSI : 1000 gates(74161 counter) LSI : 10,000 gates(8 bit µP) VLSI : > 10k gates [Moore65] Electronics Magazine

10. And Now…

11. Feature Size Minimum feature size shrinking 30% every 2-3 years

12. HKBK, Sufia Banu Corollaries Many other factors grow exponentially Ex: clock frequency, processor performance

13. MOS Transistors HKBK, Sufia Banu

14. MOS transistor as a Switch HKBK, Sufia Banu

15. CMOS LOGIC HKBK, Sufia Banu Inverter NAND Gate

16. HKBK, Sufia Banu Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network static CMOS

17. HKBK, Sufia Banu Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series N MOS : Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires either one PMOS to be ON Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel

18. Series and Parallel nMOS : 1 = ON pMOS : 0 = ON Series : both must be ON Parallel : either can be ON

19. NOR Gate HKBK, Sufia Banu

20. HKBK, Sufia Banu CMOS Gate Design Activity: Sketch a 4-input CMOS NOR gate

21. HKBK, Sufia Banu Compound Gates Compound gates can do any inverting function Ex: aaaaaaaaaaaaa AND-OR-INVERT-22 or AOI22

22. HKBK, Sufia Banu Example: O3AI

23. HKBK, Sufia Banu Signal Strength Strength of signal How close it approximates ideal voltage source V DD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network

24. HKBK, Sufia Banu Pass Transistors Transistors can be used as switches

25. Transmission Gate When an NMOS and PMOS is used alone as an imperfect switch, we call it as pass transistor. By combining NMOS and PMOS Tx in Parallel, we obtain a switch that turns ON when a ‘1’ is applied to g in which 0’s and 1’s are both passed in an acceptable fashion. It’s called as Transmission gate or Pass Gate. Both the control input and its compliment are required by the transmission gate. This is called double rail logic. HKBK, Sufia Banu

26. HKBK, Sufia Banu Tristates Tristate buffer produces Z when not enabled. When EN=1, Y follows the input A. When EN=0, Y is left floating. EN/EN. A Y 0/1 Z 0/1 1 Z 1/0 1/0 1 1

27. HKBK, Sufia Banu Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y

28. HKBK, Sufia Banu Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output

29. HKBK, Sufia Banu Multiplexers 2:1 multiplexer chooses between two inputs. It chooses input D0 if S=0 and input D1 if S=1 S D1 D0 Y X X 1 1 1 X 1 1 X 1

30. HKBK, Sufia Banu Gate-Level Mux Design How many transistors are needed? 20

31. HKBK, Sufia Banu Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors. 2 transmission gates can be tied together to form a compact 2-input MUX . The select(S) and its complement enable exactly one of the two transmission gates at any given time. S D1 D0 Y X X 1 1 1 X 1 1 X 1

32. HKBK, Sufia Banu Inverting Mux Restoring, Inverting multiplexer Use compound AOI22 as in figure 1 Or pair of tristate inverters as in figure 2 Essentially the same thing Noninverting multiplexer adds an inverter

33. HKBK, Sufia Banu 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates

34. Latches and Flip Flops HKBK, Sufia Banu

35. HKBK, Sufia Banu D Latch When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D D latch is also known as transparent latch or level-sensitive latch.

36. HKBK, Sufia Banu D Latch Design Multiplexer chooses D or old Q. D latch is also known as level sensitive Latch as the output is dependent on the level of the clock signal.

37. HKBK, Sufia Banu D Latch Operation CMOS positive-level sensitive D Latch

38. HKBK, Sufia Banu D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value It is called as positive edge-triggered flip-flop , master-slave flip-flop or D register. A negative level sensitive latch may be constructed by inverting the control connections to the multiplexers. CMOS positive-edge triggered D Flip Flop

39. HKBK, Sufia Banu Edge Triggered D Flip-flop Edge triggered flip-flop can be constructed by combining 2 level sensitive latches (one positive & one negative). Built from master and slave D latches. 1 st latch stage is called master,2 nd is called as Slave. E dge triggered D Flip Flop

40. HKBK, Sufia Banu D Flip-flop Operation

41. HKBK, Sufia Banu Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead

42. MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) – Reality: less than ideal HKBK, Sufia Banu

43. MOS Transistor Theory Study conducting channel between source and drain Modulated by voltage applied to the gate (voltage- controlled device) nMOS transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped) pMOS transistor: majority carriers are holes (less mobility), n-substrate (negatively doped) HKBK, Sufia Banu

44. Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance – I = C (  V/  t) ->  t = (C/I)  V Capacitance and current determine speed Also explore what a “degraded level” really means HKBK, Sufia Banu

45. Terminal Voltages Mode of operation depends on V g , V d , V s – V gs = V g – V s – V = V – V gd g d – V ds = V d – V s = V gs - V gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds  nMOS body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V g V s V d V gd V gs V ds + - + - + - HKBK, Sufia Banu

46. Gate Biasing n + n + S ource G ate D rain Channel + - E p-substrate SiO 2 V gs =0: no current flows from source to drain -accumulation (insulated by two reverse biased pn junctions V gs >0: electric field created across substrate V SS (Gnd) Electrons accumulate under gate: region changes from p-type to n-type (Inversion) Conduction path between source and drain HKBK, Sufia Banu

47. V gs << V t A ccu m ul ati on mode Enhancement-mode transistor (channel absent) : Conducts when gate bias V gs > V t Depletion-mode transistor (channel present) : Conducts when gate bias is zero V gs = V t Depletion mode nMOS Device Behavior p-substrate Polysilicon gate Oxide insulator V gs > V t Inversion mode Depletion region Depletion region I n v e r s io n Region (n-type) HKBK, Sufia Banu

48. nMOS Cutoff No channel I ds = + - g s V = n+ n+ + - V gd p-type body b g s d HKBK, Sufia Banu

49. nMOS Linear Channel forms Current flows from d to s – e - from s to d I ds increases with V ds Similar to linear resistor - V gs > V t + n+ n+ + - V gd = V gs + - V gs > V t n+ n+ + - V > V > V gs g d t V ds = 0 < V ds < V gs -V t p-type body p-type body b g s d b g s d I d s HKBK, Sufia Banu

50. nMOS Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source + - V gs > V t n+ n+ + - V < V g d t V ds > V gs -V t p-type body b g s d I ds HKBK, Sufia Banu

51. I-V Characteristics HKBK, Sufia Banu In linear region, I ds depends on How much charge is in the channel? How fast is the charge moving?

52. Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Q channel = n + n + + + + V gd source V gs - dra i n V ds p-type body channel - - ga te V g V s V d C g n+ n+ p-type body W L t ox SiO 2 gate oxide (good insulator,  ox = 3.9) p o l y s ili c o n gate HKBK, Sufia Banu

53. Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Q channel = CV C = n + n + + + + V gd source V gs - dra i n V ds p-type body channel - - ga te V g V s V d C g n+ n+ p-type body W L t ox SiO 2 gate oxide (good insulator,  ox = 3.9) p o l y s ili c o n gate HKBK, Sufia Banu

54. Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Q channel = CV C = C g =  ox WL/t ox = C ox WL V = n + n + + + + V gd source V gs - dra i n V ds p-type body channel - - ga te V g V s V d C g n+ n+ p-type body W L t ox SiO 2 gate oxide (good insulator,  ox = 3.9) p o l y s ili c o n gate C ox =  ox / t ox HKBK, Sufia Banu

55. Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Q channel = CV C = C g =  ox WL/t ox = C ox WL V = V gc – V t = (V gs – V ds /2) – V t n + n + + + + V gd source V gs - dra i n V ds p-type body channel - - ga te V g V s V d C g n+ n+ p-type body W L t ox SiO 2 gate oxide (good insulator,  ox = 3.9) p o l y s ili c o n gate ox HKBK, Sufia Banu C =  / t ox ox

56. Carrier velocity HKBK, Sufia Banu Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v =

57. Carrier velocity HKBK, Sufia Banu Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v =  E  called mobility E =

58. Carrier velocity HKBK, Sufia Banu Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v =  E  called mobility E = V ds /L Time for carrier to cross channel: – t =

59. Carrier velocity HKBK, Sufia Banu Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v =  E  called mobility E = V ds /L Time for carrier to cross channel: – t = L / v

60. nMOS Linear I-V HKBK, Sufia Banu Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds 

61. nMOS Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross ds HKBK, Sufia Banu I t  Q channel 

62. nMOS Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross o x HKBK, Sufia Banu 2 d s d s g s t d s d s g s t d s I t V V V  Q channel ⎞   C  V  W { | V | L ⎝ ⎠ ⎞ V   { V  V  | 2 | ⎝ ⎠ o x W L  =  C

63. nMOS Saturation I-V HKBK, Sufia Banu If V gd < V t , channel pinches off near drain – When V ds > V dsat = V gs – V t Now drain voltage no longer increases current I ds 

64. nMOS Saturation I-V If V gd < V t , channel pinches off near drain – When V ds > V dsat = V gs – V t Now drain voltage no longer increases current I ds   ⎝ | { V gs  V t HKBK, Sufia Banu  V dsat 2 | ⎞ V dsat ⎠

65. nMOS Saturation I-V If V gd < V t , channel pinches off near drain – When V ds > V dsat = V gs – V t Now drain voltage no longer increases current  HKBK, Sufia Banu 2 2 g s t I ds   ⎝ | { V gs  V t  V dsat 2 | ⎞ V dsat ⎠    V  V

66. nMOS I-V Summary  HKBK, Sufia Banu 2 cutoff l i n e a r 2 d s d s g s t d s d s d s a t g s t d s ds a t V V gs  V t | V  V I  |  { | V  V  ⎞ | V { ⎝ 2 ⎠ V  V s a t u r a t i o n | |  | ⎝  V  V Shockley 1 st order transistor models { |

67. Current-Voltage Relations HKBK, Sufia Banu

68. Current-Voltage Relations k n : transconductance of transistor W : width-to-length ratio L As W increases, more carriers available to conduct current As L increases, V ds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow HKBK, Sufia Banu

69. HKBK, Sufia Banu Ideal vs. Simulated nMOS I-V Plot 65 nm IBM process, V DD = 1.0 V

70. Transistor Operation HKBK, Sufia Banu Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in Cutoff? Linear? Saturation?

71. nMOS Operation Cutoff Linear Saturated V gsn < V gsn > V dsn < V gsn > V dsn > I dsn I dsp V HKBK, Sufia Banu o u t V DD V in

72. nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn I dsn I dsp V HKBK, Sufia Banu o u t V DD V in

73. nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn I dsn I dsp V HKBK, Sufia Banu o u t V DD V in V gsn = V in d sn V = V out

74. nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V in < V tn V in > V tn V in > V tn V dsn < V gsn – V tn V dsn > V gsn – V tn V out < V in - V tn V out > V in - V tn I dsn I dsp V HKBK, Sufia Banu o u t V DD V in V gsn = V in d sn V = V out

75. pMOS Operation Cutoff Linear Saturated V gsp > V gsp < V dsp > V gsp < V dsp < I dsn I dsp V HKBK, Sufia Banu o u t V DD V in

76. pMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp I dsn I dsp V HKBK, Sufia Banu o u t V DD V in

77. pMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp I dsn I dsp V HKBK, Sufia Banu o u t V DD V in V gsp = V in - V DD d sp V = V - V out D D V tp <

78. pMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V in > V DD + V tp V in < V DD + V tp V in < V DD + V tp V dsp > V gsp – V tp V dsp < V gsp – V tp V out > V in - V tp V out < V in - V tp I dsn I dsp V HKBK, Sufia Banu o u t V DD V in V gsp = V in - V DD d sp V = V - V out D D V tp <

79. I-V Characteristics Make pMOS wider than nMOS such that  n =  p V gsn5 V gsn4 V g s n 3 V g s n 2 V g s n 1 V gsp5 V gsp4 V gsp3 V g s p 2 V gsp1 V DD - V DD -V dsp -I dsp I dsn V dsn HKBK, Sufia Banu

80. DC Transfer Curve Transcribe points onto V in vs. V out plot C V out V in V D D V DD A B D HKBK, Sufia Banu E V t n D D V /2 V DD +V tp

81. Operating Regions Revisit transistor operating regions C V out V in V D D V DD A B D HKBK, Sufia Banu E V t n D D V /2 V DD +V tp Region nMOS pMOS A B C D E

82. Operating Regions Revisit transistor operating regions C V out V in V D D V DD A B D HKBK, Sufia Banu V tn V DD /2 E V D D + V t p Region nMOS pMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff

83. Non Ideal I-V Characteristics HKBK, Sufia Banu

84. The long-channel I-V model neglects many effects that are important to devices with channel lengths below 1 micron. The saturation current increases less than quadratically with increasing Vgs . This is caused by two effects: velocity saturation and mobility degradation. At high lateral field strengths ( Vds /L), carrier velocity ceases to increase linearly with field strength. This is called velocity saturation and results in lower Ids than expected at high Vds . At high vertical field strengths ( Vgs / tox ), the carriers scatter off the oxide interface more often, slowing their progess . This mobility degradation effect also leads to less current than expected at high Vgs . The saturation current of the nonideal transistor increases somewhat with Vds . This is caused by channel length modulation , in which higher Vds increases the size of the depletion region around the drain and thus effectively shortens the channel. The threshold voltage indicates the gate voltage necessary to invert the channel and is primarily determined by the oxide thickness and channel doping levels. However, other, fields in the transistor have some effect on the channel, effectively modifying the threshold voltage. Increasing the potential between the source and body(Vsb) raises the threshold through the body effect . Increasing the drain voltage lowers the threshold through drain-induced barrier lowering. Increasing the channel length raises the threshold through the short channel effect. Several sources of leakage result in current flow in nominally OFF transistors. When Vgs < Vt , the current drops off exponentially rather than abruptly becoming zero. This is called subthreshold conduction. The current into the gate Ig is ideally 0. HKBK, Sufia Banu

85. HKBK, Sufia Banu Mobility Degradation High E vert effectively reduces mobility Collisions with oxide interface

86. HKBK, Sufia Banu Velocity Saturation At high E lat , carrier velocity rolls off Carriers scatter off atoms in silicon lattice Velocity reaches v sat Electrons: 10 7 cm/s Holes: 8 x 10 6 cm/s Better model

87. HKBK, Sufia Banu Vel Sat I-V Effects Ideal transistor ON current increases with V DD 2 Velocity-saturated ON current increases with V DD Real transistors are partially velocity saturated Approximate with a -power law model I ds  V DD a 1 < a < 2 determined empirically ( ≈ 1.3 for 65 nm)

88. Channel Length Modulation Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a perfect current source, the p–n junction between the drain and body forms a depletion region with a width Ld that increases with Vdb , as shown in Fig. The depletion region effectively shortens the channel length to Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion L d region grows with reverse bias L eff = L – L d Shorter L eff gives more current I ds increases with V ds Even in saturation HKBK, Sufia Banu

89. Chan Length Mod I-V l = channel length modulation coefficient not feature size Empirically fit to I-V characteristics HKBK, Sufia Banu

90. HKBK, Sufia Banu Threshold Voltage Effects we have treated the threshold voltage as a constant. However, Vt increases with the source voltage, decreases with the body voltage, decreases with the drain voltage, and increases with channel length

91. HKBK, Sufia Banu Body Effect Body is a fourth transistor terminal V sb affects the charge required to invert the channel Increasing V s or decreasing V b increases V t f s = surface potential at threshold Depends on doping level N A And intrinsic carrier concentration n i g = body effect coefficient

92. HKBK, Sufia Banu Body Effect Cont. For small source-to-body voltage, treat as linear

93. HKBK, Sufia Banu DIBL Electric field from drain affects channel More pronounced in small transistors where the drain is closer to the channel Drain-Induced Barrier Lowering Drain voltage also affect V t High drain voltage causes current to increase .

94. HKBK, Sufia Banu Short Channel Effect In small transistors, source/drain depletion regions extend into the channel Impacts the amount of charge required to invert the channel And thus makes V t a function of channel length Short channel effect: V t increases with L Some processes exhibit a reverse short channel effect in which V t decreases with L

95. HKBK, Sufia Banu Leakage What about current in cutoff? Simulated results What differs? Current doesn’t go to 0 in cutoff

96. HKBK, Sufia Banu Leakage Sources Subthreshold conduction Transistors can’t abruptly turn ON or OFF Dominant source in contemporary transistors Gate leakage Tunneling through ultrathin gate dielectric Junction leakage Reverse-biased PN junction diode current

97. 1. Subthreshold Leakage The long-channel transistor I-V model assumes current only flows from source to drain when Vgs > Vt. In real transistors, current does not abruptly cut off below threshold, but rather drops off exponentially, as seen in Figure When the gate voltage is high, the transistor is strongly ON. When the gate falls below Vt , The exponential decline in current appears as a straight line on the logarithmic scale. This regime of Vgs < Vt is called weak inversion. The subthreshold leakage current increases significantly with Vds because of drain-induced barrier lowering. There is a lower limit on Ids set by drain junction leakage that is exacerbated by the negative gate voltage HKBK, Sufia Banu

98. HKBK, Sufia Banu Subthreshold Leakage Subthreshold leakage exponential with V gs n is process dependent typically 1.3-1.7 Rewrite relative to I off on log scale S ≈ 100 mV/decade @ room temperature

99. HKBK, Sufia Banu 2. Gate Leakage Carriers tunnel thorough very thin gate oxides Exponentially sensitive to t ox and V DD A and B are tech constants Greater for electrons So nMOS gates leak more Negligible for older processes (t ox > 20 Å ) Critically important at 65 nm and below (t ox ≈ 10.5 Å) From [Song01]

100. 3. Junction Leakage The p–n junctions between diffusion and the substrate or well form diodes, as shown in Figure. The well-to-substrate junction is another diode. The substrate and well are tied to GND or VDD to ensure these diodes do not become forward biased in normal operation. However, reverse-biased diodes still conduct a small amount of current. HKBK, Sufia Banu

101. HKBK, Sufia Banu Junction Leakage Reverse-biased p-n junctions have some leakage Ordinary diode leakage Band-to-band tunneling (BTBT) Gate-induced drain leakage (GIDL)

102. HKBK, Sufia Banu Diode Leakage Reverse-biased p-n junctions have some leakage At any significant negative diode voltage, I D = -I s I s depends on doping levels And area and perimeter of diffusion regions Typically < 1 fA / m m 2 (negligible)

103. HKBK, Sufia Banu Band-to-Band Tunneling Tunneling across heavily doped p-n junctions Especially sidewall between drain & channel when halo doping is used to increase V t Increases junction leakage to significant levels X j : sidewall junction depth E g : bandgap voltage A, B: tech constants

104. HKBK, Sufia Banu Gate-Induced Drain Leakage(GIDL) Occurs at overlap between gate and drain Most pronounced when drain is at V DD , gate is at a negative voltage Thwarts efforts to reduce subthreshold leakage using a negative gate voltage

105. Temperature Dependence Transistor characteristics are influenced by temperature. Carrier mobility decreases with temperature. An approximate relation is where T is the absolute temperature, Tr is room temperature, and k is a fitting parameter with a typical value of about 1.5. vsat also decreases with temperature, dropping by about 20% from 300 to 400 Ku. The magnitude of the threshold voltage decreases nearly linearly with temperature and may be approximated by where kvt is typically about 1–2 mV/K. HKBK, Sufia Banu

106. HKBK, Sufia Banu Temperature Sensitivity Increasing temperature Reduces mobility Reduces V t I ON decreases with temperature I OFF increases with temperature