Module-2 of vlsi design syatem module-2.pptx

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1. Module-2 Basics of VLSI Presented by: Dr. Vasudeva Bevara Dept. of ECE

2. Outline Driving large capacitive loads Cascaded CMOS inverters for delay optimization Wiring Capacitances Stick Diagrams Design Rules and Layout Layout Diagrams for MOS circuits Sheet resistance Gate capacitance The Delay Unit Inverter Delays Scaling models and scaling factors Scaling factors for device parameters Limitations of scaling: performance improvement by CMOS scaling.

3. MOS Layers There are 4 layers N-diffusion P-diffusion Poly Si Metal These layers are isolated by one another by thick or thin silicon dioxide insulating layers. Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.

4. Stick Diagrams A stick diagram is a cartoon of a layout. Does show all components/ vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries Key idea: "Stick figure cartoon" of a layout Useful for planning layout relative placement of transistors assignment of signals to layers connections between cells cell hierarchy

5. Stick Diagrams Metal poly ndi f f pdi f f Can also draw in shades of gray/line style.

6. Rules for Drawing Stick Diagrams Rule 1: When two or m o r e sticks o f t he sa m e t y p e cross or to u ch other that represents electrical contact.

7. Rules for Drawing Stick Diagrams Rule 2 : When two or more sticks of different type cross or touch other there is no electrical contact.(if contact is needed show explicitly)

8. Rules for Drawing Stick Diagrams Rule 3 : When a poly crosses diffusion it represents MOSFET. If contact is shown it is not transistor. nMOS F ET pMOS F ET nMOSFET (Depletion Mode)

9. Stick Diagrams PMOS Enhancement Transistor NMOS Enhancement Transistor NMOS Depletion transistor NPN Bipolar Transistor P- Diffusion n- Diffusion Poly silicon Metal 1 Contact cut N implant Demarcation line Substrate contact Buried Contact

10. nMOS Design Style: Step 1 :Draw m etal V DD an d GND r ails in parall e l leav i ng s u f fici e nt s p a c e f o r circuit components between them. V DD GND Step 2 : Thinox ( green) paths are drawn between r ails f or i nverter & inverter logic. V in V OUT V DD GND

11. nMOS Design Style: Step 3: Connect poly over thinox wherever transistor required.

12. nMOS Design Style: Step 4: Connect metal wherever is required and create contact for connection. V out V in V in V OUT V DD GND Depletion mode nMOS

13. NMOS INVERTER STICK DIAGRAM GND D A B S VDD D 5 V Dep V out E n h 0V

14. NMOS INVERTER STICK DIAGRAM 5 V Dep V out E n h 0V V V V i i n n 5 v

15. CMOS INVERTER STICK DIAGRAM VDD GND FIG 1 Supply rails

16. CMOS INVERTER STICK DIAGRAM VDD PMOS NMOS S S D D Fig 2 Drawing Pmos and Nmos Transistors between Supply rails GND

17. CMOS INVERTER STICK DIAGRAM GND VDD PMOS NMOS A D S S D Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1

18. CMOS INVERTER STICK DIAGRAM VDD PMOS NMOS D A S S D B GND Fig 6 Connect the source of Pmos to VDD and Nmos to GND

19. CMOS INVERTER STICK DIAGRAM VDD PMOS NMOS D A S S D B CO N T ACT GND Fig 7 Connect the contact cuts where the different metals are connected Substrate contact

20. CMOS INVERTER STICK DIAGRAM Gnd Vp x x X x Vp Gnd X x X X

21. CMOS NAND GATE STICK DIAGRAM Sc h e m atic VDD GND Supply rails Gnd V DD a . b a b

22. CMOS NAND GATE STICK DIAGRAM VDD GND Drawing P and N Diffusion between Supply rails

23. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Drawing the poly silicon for two different inputs and identify the source and drain

24. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Connect the source of Pmos to VDD and Nmos to GND and subtrate contacts of both

25. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Draw the output connections

26. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Draw the output connections Gnd V DD a . b a b

27. CMOS NOR GATE STICK DIAGRAM

28. CMOS NOR GATE STICK DIAGRAM

29. Encodings for NMOS process:

30. Dr. Vasudeva 30 Department of Electronics and Communication Engineering, MREC Encodings for CMOS process: Figure shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows when a p- transistor is formed: a transistor is formed when a yellow line(p+ diffusion) crosses a red line (poly) completely

31. Dr. Vasudeva 31 Department of Electronics and Communication Engineering, MREC Encoding for BJT and MOSFETs: layers in an nMOS chip consists of a p-type substrate paths of n-type diffusion a thin layer of silicon dioxide paths of polycrystalline silicon a thick layer of silicon dioxide paths of metal (usually aluminium) a further thick layer of silicon dioxide

32. L A YOUT

33. There are primarily two approaches in describing the design rules Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen that a design can be easily ported over a cross section of industrial process ,making the layout portable . Scaling can be easily done by simply changing the value . Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the design rules are expressed in absolute dimensions (e.g.0.75μm) and therefore can exploit the features of a given process to a maximum degree. What is Via? It is used to connect higher level metals from metal1 connection T h e dir e ct conn e ctio n s betwee n metal, polysil i con, an d diffusio n use intermediate layers such as the contact-cut and the buried-contact layers. T h e en t ire chip is t ypical ly covered with a layer o f protectiv e coat i n g called overglass

34. Department of Electronics and Communication Engineering, MREC 3 λ 2λ 1λ 2λ 3λ P diffusion N diffusion P diffusion P diffusion N diffusion P diffusion METAL 1 METAL 1 4λ 4λ 3λ Department of Electronics and Communication Engineering, MREC

35. Transistor Layout 1 2 5 3 Transistor Department of Electronics and Communication Engineering, MREC

36. Via’s and Contacts 1 2 1 V i a Metal to Poly Contact Metal to Active Contac t 1 2 5 4 3 2 2 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

37. Select Layer 1 3 3 2 2 2 W e l l Substrate S e l e ct 3 5 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

38. 2λ 4λ 4λ 1λ 2λ 4λ 4λ 1λ 2λ 3λ Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

39. 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 6λ x 6λ 2λ 2λ 2λ 2λ 2λ NMOS ENHANCEMENT PMOS ENHANCEMENT NMOS DEPLE T I ON Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

40. Lambda based Design Rules: Design rules include width rules and spacing rules. Mead and Conway developed a set of simplified scalable λ -based design rules, which are valid for a range of fabrication technologies. In these rules, the minimum feature size of a technology is characterized as 2 λ . All width and spacing rules are specified in terms of the parameter λ . Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

41. Design rules for the diffusion layers and metal layers Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and p diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ. Similarly it shows for other layers. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

42. Design rules for transistors and gate over hang distance Figure shows the design rule for the transistor, and it also shows that the poly should extend for a minimum of 2λ beyond the diffusion boundaries.(gate over hang distance) Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

43. Design rules for contact cuts Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

44. V ia VIA is used to connect higher level metals from metal1 connection. Figure shows the design rules for contact cuts and Vias. The design rule for contact is minimum 2λx2λ and same is applicable for a Via. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

45. Buried contact and Butting contact Buried contact is made down each layer to be joined Butting contact The layers are butted together in such a way the two contact cuts become contiguous Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

46. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

47. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC Contd..

48. SCHEMATIC AND LAYOUT OF BASIC GATES a) CMOS INVERTER NOT GATE Schematic Stick diagram Layout Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

49. Example: Inverter Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

50. The CMOS NOT Gate X X X X Vp Gnd x Gnd n - w e l l Vp x x x Contact Cut Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

51. Alternate Layout of NOT Gate Gnd Vp x x X x Vp Gnd X x X X Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

52. b) NAND GATE Schematic Stick diagram Layout Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

53. NAND2 Layout Gnd Vp a . b a b X Vp Gnd X X X X a b a . b Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

54. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

55. NOR2 Layout Gnd Vp a  b a b X Vp Gnd X X X X a b a  b Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

56. Inverter, contd.. Layout using Electric Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

57. Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 by 40 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

58. NAND3 (using Electric), contd. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

59. Scaling VLSI technology is constantly evolving towards smaller line widths Reduced feature size generally leads to better / faster performance More gate / chip More accurate description of modern technology is ULSI (ultra large scale integration Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

60. Scaling Factors In our discussions we will consider 2 scaling factors, α and β 1/ β is the scaling factor for VDD and oxide thickness D 1/ α is scaling factor for all other linear dimensions We will assume electric field is kept constant Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

61. Scaling Factors for Device Parameters Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125 - 129 It is important that you understand how the following parameters are effected by scaling. Gate A r ea Gate Capacitance per unit area Gate Capacitance Charge in Channel Channel Resistance Transistor Delay Maximum Operating Frequency Transistor Current Switching Energy Power Dissipation Per Gate (Static and Dynamic) Power Dissipa t i o n Per U nit A r ea Power - Speed Product Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

62. MOSFET Scaling Constant Field Scaling Constant Voltage Scaling Lateral Scaling SCALING - refers to ordered reduction in dimensions of the MOSFET and other VLSI features Reduce Size of VLSI chips. Change operational characteristics of MOSFETs and parasitic. Physical limits restrict degree of scaling that can be achieved. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

63. Constant Voltage Scaling V dd is kept constant. All dimensions, including those vertical to the surface are scaled. Concentration densities are scaled. Dr. Vasudeva

64. Lateral Scaling Only the gate length is scaled L = 1/ α (gate-shrink). ❑ Year Feature Size( μ m) 1980 5.0 1983 3.5 1985 2.5 1987 1.75 1989 1.25 1991 1.0 1993 0.8 1995 0.6 Dr. Vasudeva

65. PARAMETER SCALING MODEL Constant Constant Lateral Length (L) Field Voltage 1/ α 1/ α 1/ α Width (W) 1/ α 1/ α 1 Supply Voltage (V) 1/ α 1 1 Gate Oxide thickness (tox) 1/ α 1/ α 1 Junction depth (Xj) 1/ α 1/ α 1 Current (I) 1/ α α α Power Dissipation (P) 1/ α 2 α α Electric Field 1 α 1 Load Capacitance (C) Gate Delay (T) 1/ α 1/ α 1/ α 1/ α 2 1/ α 1/ α 2 Dr. Vasudeva

66. Scaling of Interconnects Resistance of track R ~ L / wt R (scaled) ~ (L / α) / ( (w/ α )* (t /α)) R(scaled) = αR therefore resistance increases with scaling t w L A B Dr. Vasudeva

67. Scaling - Time Constant Time constant of track connected to gate, T = R * Cg T(scaled) = α R * (β / α 2 ) *Cg = (β / α) *R*Cg Let β = α, therefore T is unscaled! Therefore delays in tracks don’t reduce with scaling Therefore as tracks get proportionately larger, effect gets worse Cross talk between connections gets worse because of reduced spacing Dr. Vasudeva

68. Scaling of MOS and circuit parameter Dr. Vasudeva