Module-2 stick diagram and layout in VLSI.pptx

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1. Module-2 Basics of VLSI Presented by: Dr. Vasudeva Bevara Dept. of ECE

2. Outline Driving large capacitive loads Cascaded CMOS inverters for delay optimization Wiring Capacitances Stick Diagrams Design Rules and Layout Layout Diagrams for MOS circuits Sheet resistance Gate capacitance The Delay Unit Inverter Delays Scaling models and scaling factors Scaling factors for device parameters Limitations of scaling: performance improvement by CMOS scaling.

3. MOS Layers There are 4 layers N-diffusion P-diffusion Poly Si Metal These layers are isolated by one another by thick or thin silicon dioxide insulating layers. Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.

4. Stick Diagrams A stick diagram is a cartoon of a layout. Does show all components/ vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries Key idea: "Stick figure cartoon" of a layout Useful for planning layout relative placement of transistors assignment of signals to layers connections between cells cell hierarchy

5. Stick Diagrams Metal poly ndi f f pdi f f Can also draw in shades of gray/line style.

6. Rules for Drawing Stick Diagrams Rule 1: When two or m o r e sticks o f t he sa m e t y p e cross or to u ch other that represents electrical contact.

7. Rules for Drawing Stick Diagrams Rule 2 : When two or more sticks of different type cross or touch other there is no electrical contact.(if contact is needed show explicitly)

8. Rules for Drawing Stick Diagrams Rule 3 : When a poly crosses diffusion it represents MOSFET. If contact is shown it is not transistor. nMOS F ET pMOS F ET nMOSFET (Depletion Mode)

9. Stick Diagrams PMOS Enhancement Transistor NMOS Enhancement Transistor NMOS Depletion transistor NPN Bipolar Transistor P- Diffusion n- Diffusion Poly silicon Metal 1 Contact cut N implant Demarcation line Substrate contact Buried Contact

10. nMOS Design Style: Step 1 :Draw m etal V DD an d GND r ails in parall e l leav i ng s u f fici e nt s p a c e f o r circuit components between them. V DD GND Step 2 : Thinox ( green) paths are drawn between r ails f or i nverter & inverter logic. V in V OUT V DD GND

11. nMOS Design Style: Step 3: Connect poly over thinox wherever transistor required.

12. nMOS Design Style: Step 4: Connect metal wherever is required and create contact for connection. V out V in V in V OUT V DD GND Depletion mode nMOS

13. NMOS INVERTER STICK DIAGRAM GND D A B S VDD D 5 V Dep V out E n h 0V

14. NMOS INVERTER STICK DIAGRAM 5 V Dep V out E n h 0V V V V i i n n 5 v

15. CMOS INVERTER STICK DIAGRAM VDD GND FIG 1 Supply rails

16. CMOS INVERTER STICK DIAGRAM VDD PMOS NMOS S S D D Fig 2 Drawing Pmos and Nmos Transistors between Supply rails GND

17. CMOS INVERTER STICK DIAGRAM GND VDD PMOS NMOS A D S S D Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1

18. CMOS INVERTER STICK DIAGRAM VDD PMOS NMOS D A S S D B GND Fig 6 Connect the source of Pmos to VDD and Nmos to GND

19. CMOS INVERTER STICK DIAGRAM VDD PMOS NMOS D A S S D B CO N T ACT GND Fig 7 Connect the contact cuts where the different metals are connected Substrate contact

20. CMOS INVERTER STICK DIAGRAM Gnd Vp x x X x Vp Gnd X x X X

21. CMOS NAND GATE STICK DIAGRAM Sc h e m atic VDD GND Supply rails Gnd V DD a . b a b

22. CMOS NAND GATE STICK DIAGRAM VDD GND Drawing P and N Diffusion between Supply rails

23. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Drawing the poly silicon for two different inputs and identify the source and drain

24. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Connect the source of Pmos to VDD and Nmos to GND and subtrate contacts of both

25. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Draw the output connections

26. CMOS NAND GATE STICK DIAGRAM VDD S S S D D D D S A B C GND Draw the output connections Gnd V DD a . b a b

27. CMOS NOR GATE STICK DIAGRAM

28. CMOS NOR GATE STICK DIAGRAM

29. Encodings for NMOS process:

30. Dr. Vasudeva 30 Department of Electronics and Communication Engineering, MREC Encodings for CMOS process: Figure shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows when a p- transistor is formed: a transistor is formed when a yellow line(p+ diffusion) crosses a red line (poly) completely

31. Dr. Vasudeva 31 Department of Electronics and Communication Engineering, MREC Encoding for BJT and MOSFETs: layers in an nMOS chip consists of a p-type substrate paths of n-type diffusion a thin layer of silicon dioxide paths of polycrystalline silicon a thick layer of silicon dioxide paths of metal (usually aluminium) a further thick layer of silicon dioxide

32. L A YOUT

33. There are primarily two approaches in describing the design rules Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen that a design can be easily ported over a cross section of industrial process ,making the layout portable . Scaling can be easily done by simply changing the value . Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the design rules are expressed in absolute dimensions (e.g.0.75μm) and therefore can exploit the features of a given process to a maximum degree. What is Via? It is used to connect higher level metals from metal1 connection T h e dir e ct conn e ctio n s betwee n metal, polysil i con, an d diffusio n use intermediate layers such as the contact-cut and the buried-contact layers. T h e en t ire chip is t ypical ly covered with a layer o f protectiv e coat i n g called overglass

34. Department of Electronics and Communication Engineering, MREC 3 λ 2λ 1λ 2λ 3λ P diffusion N diffusion P diffusion P diffusion N diffusion P diffusion METAL 1 METAL 1 4λ 4λ 3λ Department of Electronics and Communication Engineering, MREC

35. Transistor Layout 1 2 5 3 Transistor Department of Electronics and Communication Engineering, MREC

36. Via’s and Contacts 1 2 1 V i a Metal to Poly Contact Metal to Active Contac t 1 2 5 4 3 2 2 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

37. Select Layer 1 3 3 2 2 2 W e l l Substrate S e l e ct 3 5 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

38. 2λ 4λ 4λ 1λ 2λ 4λ 4λ 1λ 2λ 3λ Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

39. 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 6λ x 6λ 2λ 2λ 2λ 2λ 2λ NMOS ENHANCEMENT PMOS ENHANCEMENT NMOS DEPLE T I ON Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

40. Lambda based Design Rules: Design rules include width rules and spacing rules. Mead and Conway developed a set of simplified scalable λ -based design rules, which are valid for a range of fabrication technologies. In these rules, the minimum feature size of a technology is characterized as 2 λ . All width and spacing rules are specified in terms of the parameter λ . Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

41. Design rules for the diffusion layers and metal layers Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and p diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ. Similarly it shows for other layers. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

42. Design rules for transistors and gate over hang distance Figure shows the design rule for the transistor, and it also shows that the poly should extend for a minimum of 2λ beyond the diffusion boundaries.(gate over hang distance) Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

43. Design rules for contact cuts Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

44. V ia VIA is used to connect higher level metals from metal1 connection. Figure shows the design rules for contact cuts and Vias. The design rule for contact is minimum 2λx2λ and same is applicable for a Via. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

45. Buried contact and Butting contact Buried contact is made down each layer to be joined Butting contact The layers are butted together in such a way the two contact cuts become contiguous Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

46. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

47. Dr. Vasudeva Department of Electronics and Communication Engineering, MREC Contd..

48. SCHEMATIC AND LAYOUT OF BASIC GATES a) CMOS INVERTER NOT GATE Schematic Stick diagram Layout Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

49. Example: Inverter Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

50. The CMOS NOT Gate X X X X Vp Gnd x Gnd n - w e l l Vp x x x Contact Cut Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

51. Alternate Layout of NOT Gate Gnd Vp x x X x Vp Gnd X x X X Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

52. b) NAND GATE Schematic Stick diagram Layout 52 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

53. NAND2 Layout Gnd Vp a . b a b X Vp Gnd X X X X a b a . b 53 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

54. 54 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

55. NOR2 Layout Gnd Vp a  b a b X Vp Gnd X X X X a b a  b 55 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

56. Inverter, contd.. Layout using Electric Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

57. Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 by 40 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

58. NAND3 (using Electric), contd. 58 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

59. Scaling VLSI technology is constantly evolving towards smaller line widths Reduced feature size generally leads to better / faster performance More gate / chip More accurate description of modern technology is ULSI (ultra large scale integration Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

60. Scaling Factors In our discussions we will consider 2 scaling factors, α and β 1/ β is the scaling factor for VDD and oxide thickness D 1/ α is scaling factor for all other linear dimensions We will assume electric field is kept constant 60 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

61. Scaling Factors for Device Parameters Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125 - 129 It is important that you understand how the following parameters are effected by scaling. Gate A r ea Gate Capacitance per unit area Gate Capacitance Charge in Channel Channel Resistance Transistor Delay Maximum Operating Frequency Transistor Current Switching Energy Power Dissipation Per Gate (Static and Dynamic) Power Dissipa t i o n Per U nit A r ea Power - Speed Product Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

62. MOSFET Scaling Constant Field Scaling Constant Voltage Scaling Lateral Scaling SCALING - refers to ordered reduction in dimensions of the MOSFET and other VLSI features Reduce Size of VLSI chips. Change operational characteristics of MOSFETs and parasitic. Physical limits restrict degree of scaling that can be achieved. 62 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

63. Constant Field Scaling The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scale- factor α (such that E is unchanged): all dimensions, including those vertical to the surface (1/ α ) device voltages (1/ α ) the concentration densities ( α ) . 63 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

64. Constant Voltage Scaling V dd is kept constant. All dimensions, including those vertical to the surface are scaled. Concentration densities are scaled. 64 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

65. Lateral Scaling Only the gate length is scaled L = 1/ α (gate-shrink). ❑ Year Feature Size( μ m) 1980 5.0 1983 3.5 1985 2.5 1987 1.75 1989 1.25 1991 1.0 1993 0.8 1995 0.6 65 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

66. PARAMETER SCALING MODEL Constant Constant Lateral Length (L) Field Voltage 1/ α 1/ α 1/ α Width (W) 1/ α 1/ α 1 Supply Voltage (V) 1/ α 1 1 Gate Oxide thickness (tox) 1/ α 1/ α 1 Junction depth (Xj) 1/ α 1/ α 1 Current (I) 1/ α α α Power Dissipation (P) 1/ α 2 α α Electric Field 1 α 1 Load Capacitance (C) Gate Delay (T) 1/ α 1/ α 1/ α 1/ α 2 1/ α 1/ α 2 66 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

67. Scaling of Interconnects Resistance of track R ~ L / wt R (scaled) ~ (L / α) / ( (w/ α )* (t /α)) R(scaled) = αR therefore resistance increases with scaling t w L A B 67 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

68. Scaling - Time Constant Time constant of track connected to gate, T = R * Cg T(scaled) = α R * (β / α 2 ) *Cg = (β / α) *R*Cg Let β = α, therefore T is unscaled! Therefore delays in tracks don’t reduce with scaling Therefore as tracks get proportionately larger, effect gets worse Cross talk between connections gets worse because of reduced spacing 68 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

69. Scaling of MOS and circuit parameter 69 Dr. Vasudeva Department of Electronics and Communication Engineering, MREC

70. IC Technology Indentify the Image Early developments of the Integrated Circuit (IC) go back to 1949. German engineer Werner Jacobi filed a patent for an IC like semiconductor amplifying device showing five transistors on a common substrate in a 2-stage amplifier arrangement. Jacobi disclosed small cheap of hearing aids . Invention

71. Inventor Year Circuit Remark Fleming 1904 1906 Vacuum tube diode Vacuum triode large expensive, power- hungry, unreliable William Shockley (Bell labs) 1945 Semiconductor replacing vacuum tube Bardeen and Brattain and Shockley (Bell labs) 1947 Point Contact transfer resistance device “BJT” Driving factor of growth of the VLSI technology Werner Jacobi ( Sie m ens A G ) 1949 1 st IC containing amplifying Device 2stage amplifier No commercial use reported Shockley 1951 Junction Transistor “Practical form of transistor” Jack Kilby (Texas Instruments) July 1958 Integrated Circuits F/F With 2-T Germanium slice and gold wires Father of IC design Fairchild Semi c on d uctor And Texas 1061 First Commercial IC Frank Wanlass (Fairchild Semiconductor) 1963 CMOS Federico Faggin (Fairchild Semiconductor) 1968 Silicon gate IC technology Later Joined Intel to lead first CPU Intel 4004 in 1970 2300 T on 9mm 2

72. 1965 - Moore's law Indentify the Image Gordon E. Moore - Chairman Emeritus of Intel Corporation 1965 - observed trends in industry - of transistors on ICs vs. release dates : Noticed number of transistors doubling with release of each new IC generation release dates (separate generations) were all 18-24 months apart Moore’s Law: “The number of transistors on an integrated circuit will double every 18 months” The level of integration of silicon technology as measured in terms of number of devices per IC Semiconductor industry has followed this prediction with surprising accuracy. "Cramming more components onto integrated circuits".

73. 1965 - Moore's law Indentify the Image

74. Discrete vs Integrated Circuit Design Indentify the Image Activity/Item Discrete circuits Integrated Circuits Co m ponent Accuracy Well Known Poor a bsolute Accurac i es Bread boarding Yes No Fabrication Independent Very dependent Physical Implementation PC Layout Layout, verification and Extraction Parasitic Not important Must be included in the design Simulation Model Parameters well known Model parameters vary widely Testing Generally complete testing is possible Must be considered before design CAD Schematic capture Simulation, PC Board layout Schematic capture Simulation, layout Components All possible Active devices, capacitor, and resistor

75. Indentify the Image IC Technology Bipolar CMOS BiCMOS SOI SiGe GaAs Category BJT CMOS Power Dissipation Moderate to High less Speed Faster Fast Gm 4ms 0.4ms Switch implement a t i on poor Good Technology improve m ent slower Faster Why C M O S ? Lower Power D i ssip a ti o n High p a c ki n g density Scale down more easily Fully restored logic levels Appr. Equal rise and fall time

76. Indentify the Image

77. MOSFETs Indentify the Image

78. Depletion-Type MOSFET Construction Indentify the Image

79. B asic Operation Indentify the Image

80. Enhancement-Type MOSFET Construction Indentify the Image

81. Basic Operation and Characteristics Indentify the Image

82. Continued… Indentify the Image

83. Continued… Indentify the Image Eventually, the channel will be reduced to the point of pinch-off and a saturation condition will be established.

84. Continued… Indentify the Image

85. MOSFET Symbols Indentify the Image

86. MOSFET vs BJT Indentify the Image MOSFET applications Radiofrequency applications use MOSFET amplifiers extensively. MOSFET behaves as a passive circuit element. Power MOSFETs can be used to regulate DC motors. MOSFETs are used in the design of the chopper circuit. Advantages of MOSFET MOSFETs operate at greater efficiency at lower voltages. Absence of gate current results in high input impedance producing high switching speed. Disadvantages of MOSFET MOSFETs are vulnerable to damage by electrostatic charges due to the thin oxide layer. Overload voltages make MOSFETs unstable.

87. MOSFET vs BJT Indentify the Image

88. Fabrication Processes Indentify the Image The basic fabrication processes of the Integrated Circuits

89. Sand / Ingot Indentify the Image Sand Silicon is the second most abundant element in the earth's crust. Common sand has a high percentage of silicon. Silicon – the starting material for computer chips – is a semiconductor, meaning that it can be readily turned into an excellent conductor or an insulator of electricity, by the introduction of minor amounts of impurities. Melted Silicon – scale: wafer level (~300mm / 12 inch) In order to be used for computer chips, silicon must be purified so there is less than one alien atom per billion. It is pulled from a melted state to form a solid which is a single, continuous and unbroken crystal lattice in the shape of a cylinder, known as an ingot. Monocrystalline Silicon Ingot – scale: wafer level (~300mm / 12 inch) The ingot has a diameter of 300mm and weighs about 100 kg.

90. Wafer Preparation Indentify the Image The wafer preparation is the first step for IC fabrication. It involves cutting, shaping, and polishing the wafer material to make it suitable for further fabrication. Some wafers are modified because of their sharp edges, irregular surface, and shape to convert them to the required wafer. A wafer is a thin material used for making various Integrated circuits and transistors. Wafer acts as a base for such devices. The material of a wafer is the semiconductor, especially crystalline silicon. The silicon crystals used for the wafer manufacturing are highly pure. The process of extracting pure metal from the melt is known as a boule. The impurities are further added to the molten state of the material in a specific amount to make it n-type or p- type.

91. Oxidation – Create Oxide Film on Wafer Surface Indentify the Image Oxidation is the process of adding oxygen. In a semiconductor, the oxygen and the silicon react to form silicon dioxide. The oxidation is carried out in furnaces at high temperatures up to 1250 degrees Celsius. Oxidation is classified as wet oxidation or dry oxidation. Both processes are widely used and have their own advantages and disadvantages. Wet oxidation is fast, while dry oxidation has good electrical properties. Wet oxidation is also known as steam . Both types of oxidation have excellent electrical insulation properties. The deposition of silicon dioxide on the silicon wafer protects from many impurities. The dopants can be applied only to areas not covered with the SiO2.

92. Photolithography – Draw Circuit Design on Wafer Indentify the Image A p plyi n g P h o t o res ist – Photolithograp h y is the proc ess b y whi c h a sp ecific pa t tern is imprinted on the wafer. It st art s wit h the appl ication of a liquid known as photoresist, which is evenly poure d onto the wafer while it spins. It gets its name from the fact that it is sensitive to certain frequencies of light (“pho t o”) an d is resis tant to cer tai n ch emicals that will b e used later to re m ove portion s of a layer of material (“resist”). E x p o s u re – Th e photores i st is hardened, an d portion s of it ar e exposed to ultraviolet (UV) light, making it soluble. Th e exposure is don e using masks that ac t like st encils, so only a sp ecific pa t tern of photores i st become s soluble. Th e mask has a n image of the pa t tern that needs to g o on the wafer; it is opti call y reduced by a lens, and the exposure tool steps and repeats acr oss the wafer to for m the same image a large nu m be r of ti mes. R e s i s t D e ve l o pm e n t – Th e soluble photores i st is remo ved b y a chemical process, leaving a photoresist pa t tern de t er m ined b y what was on the mask. Next step is to draw a circuit design onto a wafer which is called the photolithography process. A photo mask functions as the film. A photo mask is a glass substrate with a computer designed circuit pattern.

93. Ion Implantation Indentify the Image Ion Implantation– The wafer with patterned photoresist is bombarded with a beam of ions (positively or negatively charged atoms) which become embedded beneath the surface in the regions not covered by photoresist. This process is called doping, because impurities are introduced into the silicon. This alters the conductive properties of the silicon (making it conductive or insulating, depending on the type of ion used) in selected locations. Removing Photoresist– After ion implantation, the photoresist is removed and the resulting wafer has a pattern of doped regions in which transistors will be formed. Begin Transistor Formation– Here we zoom into a tiny part of the wafer, where a single transistor will be formed. The green region represents doped silicon. Today’s wafers can have hundreds of billions of such regions which will house transistors. Next step is to draw a circuit design onto a wafer which is called the photolithography process. A photo mask functions as the film. A photo mask is a glass substrate with a computer designed circuit pattern.

94. Ion Implantation Indentify the Image Diffusion is a process of adding impurities atoms from a region with high concentration to a region of low concentration. The dopants or impurity atoms are added to the silicon (semiconductor material), which changes its resistivity. Coating the thin film at a desired molecular or atomic level onto a wafer is called deposition. Since the coating is so thin, precise and sophisticated technology is required to uniformly apply the thin film on a wafer to give the semiconductor electrical characteristics. Ion implementation / Ion implantation is also required.

95. Etching – Remove Unnecessary Materials Indentify the Image Etch– In order to create a fin for a tri-gate transistor, a pattern of material called a hard mask (blue) is applied using the photolithography process just described. Then a chemical is applied to etch away unwanted silicon, leaving behind a fin with a layer of hard mask on top. Removing Photoresist – The hard mask is chemically removed, leaving a tall, thin silicon fin which will contain the channel of a transistor. Now it is time to remove unnecessary materials from the wafer surface so that only the design pattern remains. Wet Etching: When chemical solutions are used for etching, it is called wet etching. Dry Etching: When gas or plasma is used, it is called dry etching. This is done using a liquid or gas etching technique. All unnecessary materials are selectively removed to draw the desired design.

96. Metal Deposition (Metallization) Ready Transistor – This transistor is close to being finished. Three holes have been etched into the insulation layer (red color) above the transistor. These three holes will be filled with copper or other material which will make up the connections to other transistors. Electroplating – The wafers are put into a copper sulphate solution at this stage. The copper ions are deposited onto the transistor thru a process called electroplating. The copper ions travel from the positive terminal (anode) to the negative terminal (cathode) which is represented by the wafer. After Electroplating – On the wafer surface the copper ions settle as a thin layer of copper.

97. Wafer Sort / Singulation Wafer Sort – This portion of a ready wafer is being put through a test. A tester steps across the wafer; leads from its head make contact on specific points on the top of the wafer and an electrical test is performed. Test patterns are fed into every single chip and the response from the chip is monitored and compared to “the right answer”. Wafer Slicing – The wafer is cut into pieces (called die). The above wafer contains future Intel processors codenamed Ivy Bridge. Selecting Die for Packaging – The die that responded with the right answer to the test patterns will be packaged.

98. Encapsulation or Packaging Individual Die – These are individual die which have been cut out in the previous step (singulation). The die shown here is Intel’s first 22nm microprocessor codenamed Ivy Bridge. Packaging – The package substrate, the die and the heat spreader are put together to form a completed processor. The green substrate builds the electrical and mechanical interface for the processor to interact with the rest of the PC system. The silver heat spreader is a thermal interface which helps dissipate heat. Processor – Completed processor (Ivy Bridge in this case). A microprocessor has been called the most complex manufactured product made by man. In fact, it takes hundreds of steps – only the most important ones have been included in this picture story - in the world's cleanest environment (a microprocessor fab).

99. Semiconductor Manufacturing Process Flow Chart

100. N-MOS Fabrication Process Fig. (1) Pure Si single crystal Si-substrate Fig. (2) P-type impurity is lightly doped - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - F i g . (3) SiO 2 D e po s i te d o v er s i s u rface Fig. (4) Photoresist is deposited over SiO 2 layer Photoresist Th ick SiO 2 (1 µ m) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

101. N-MOS Fabrication Process Mask-1 is used to expose the SiO 2 where S, D and G is to be formed. Fig. (5) Photoresist layer is exposed to UV Light through a mask - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Mask-1 Photoresist Th ick SiO 2 (1 µm) U V L i gh t

102. N-MOS Fabrication Process Fig. (6) Etching [HF acid is used] will remove SiO2 layer which is in direct contact with etching solution Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Fig. (7) unpolymerised photoresist is also etched away [ u si n g H 2SO4] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm)

103. N-MOS Fabrication Process F i g . (1 ) A l a y e r o f pho t or es i st i s g r o w n o v er po l y s ili c o n l a y e r Th ick SiO 2 (1 µm) Th in SiO 2 (0.1 µ m) P o l y silic o n layer Photoresist - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

104. N-MOS Fabrication Process M as k - 2 i s u sed to d e po s i t Polysilicon to form gate. F i g . ( 1 1 ) P ho t or es i s t i s ex po s ed to U V L i gh t U V L i gh t M as k- 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

105. N-MOS Fabrication Process Fig. (12) Etching will remove that portion of Thin SiO2 which is not exposed to UV light Th ick SiO 2 (1 µm) Th in SiO 2 (0.1 µ m) Polysilicon - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Fig. (13) Polymerised photoresist is also stripped away Th in SiO 2 (0.1 µ m) P o l y sili c o n u sed a s G A T E (1 – 2 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

106. N-MOS Fabrication Process Fig. (14) n + Doping to form SOURCE and DRAIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) Th in SiO 2 (0.1 µ m) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - G A T E - - - - - - n+ SO URC E DR A I N F i g . (15) A t h i c k l a y e r o f SiO2 (1 µ m) is a g ain g r o w n . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) Step - Metallization

107. N-MOS Fabrication Process Fig. (16) Photoresist is grown over thick SiO 2 . Selected areas of the poly GATE and SOURCE and DRAIN are exposed where contact cuts are to be made - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) Mask-3 Mask-3 is used to make contact cuts for S, D and G. Photoresist U V Lig h t Step - Metallization

108. N-MOS Fabrication Process Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This unpolymerised photoresist and SiO 2 below it are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) Mask-3 P ho t o resist

109. N-MOS Fabrication Process Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) Mask-3 P ho t o resist

110. N-MOS Fabrication Process Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 µm thickness). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) M e t a l ( 1 µ m)

111. N-MOS Fabrication Process Fig. (20) Photoresist is deposited over the metal. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) M e t a l ( 1 µ m) Photoresist

112. N-MOS Fabrication Process Mask-4 is used to deposit metal in contact cuts of S, D and G. Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in contact-cuts). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) Mask-4 Photoresist M e t a l ( 1 µ m) U V L i gh t

113. N-MOS Fabrication Process Fig. (22) Photoresist and metal which is not exposed to UV light are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Th ick SiO 2 (1 µm) - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ Th ick SiO 2 (1 µm) Mask-4 Photoresist M e t a l (1 µ m)

114. N-MOS Fabrication Process F i g . (23) F i n al n - M OS T r a n s i st o r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - n+ - - - - - - - - - n+ SO URC E DR A I N G A T E

115. P-MOS Fabrication Process

116. CMOS (Complementary Metal Oxide Semiconductor) In CMOS technology, both N-type and P-type transistors are used to design logic functions. In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network between the output and the low voltage power supply rail ( Vss or quite often ground). The same signal which turns ON a transistor of one type is used to turn OFF a transistor of the other type. This characteristic allows the design of logic devices using only simple switches, without the need for a pull-up resistor

117. CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

118. Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y G N D V DD n+ p+ SiO 2 n+ diffusion p+ diffusion polysilicon m e t a l1 nMOS transistor pMOS transistor

119. Well and Substrate Taps n+ p substrate p+ n well Y Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps A GND V DD n+ p+ substrate tap well tap n+ p+

120. Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line G N D V DD Y A substrate tap well tap nMOS transistor pMOS transistor

121. Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal M e t a l P o l y silic o n Contact n + D iff u sion p + D iff u sion n w e ll

122. Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2 p substrate

123. Oxidation & Photoresist Grow SiO 2 on top of Si wafer 900 – 1200 C with H 2 O or O 2 in oxidation furnace Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

124. Lithography Expose photoresist through n-well mask Strip off exposed photoresist

125. Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

126. Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step

127. n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO 2 , only enter exposed Si

128. Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

129. Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor

130. Polysilicon Patterning Use same lithography process to pattern polysilicon

131. Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

132. N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

133. N-diffusion cont. Historically dopants were diffused Usually, ion implantation today But regions are still called diffusion

134. P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

135. Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

136. Metallization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

137. Latch-UP What is Latch-up? Latch-up is a condition that can occur in a circuit fabricated in a bulk CMOS technology. When a chip is in a state of latch –up it draws a large current from the power supply but does not function in response to input stimuli. A chip may be operating normally and then enter a state of latch-up; in this case, removing and reconnecting the power supply may restore operations. In other words Latch-up is the creation of a low impedance path between the power supply rails. • Latch-up is caused by the triggering of parasitic bipolar structures within an integrated circuit when applying a current or voltage stimulus on an input, output, or I/O pin or by an over-voltage on the power supply pin.

138. Latch-up in CMOS Shown alongside is a CMOS transistor consisting of an NMOS and a PMOS device. Q1 and Q2 are parasitic transistor elements residing inside it. Q1 is double emitter pnp transistor whose base is formed by n well substrate of PMOS, two emitters are formed by source and drain terminal of PMOS and collector is formed by substrate(p type) of NMOS. The reverse is true for Q2. The two parasitic transistors form a positive feedback loop and is equivalent to an SCR (as stated earlier).

139. Techniques to minimize latchup sensitivity Increasing PMOS-NMOS spacing Guard rings to form additional collectors for the parasitic transistors CMOS processes: Epitaxial layer instead of bulk CMOS Retrograde well Oxide trenches between the NMOS and PMOS devices www.analog.com