Module1_DDCO_Final-----------------.pptx

1. 1 By, Dr. Ashwini N Assistant Professor Dept. of Information Science & Engineering BMS Institute of Technology, Bengaluru . Digital design and computer organization BCS302 Module 1 Introduction to Digital Design

2. Basic Gates A logic gate is a digital circuit with 1 or more input voltages but only 1 output voltage. Logic gates are the fundamental building blocks of digital systems. By connecting the different gates in different ways, we can build circuits that perform arithmetic and other functions associated with the human brain. Because the circuits simulate mental processes, gates are often called logic circuits . NOT, OR & AND gates are the basic types of gates. The inter-connection of gates to perform a variety of logical operations is called logic design. The operation of a logic gate can be easily understood with the help of "truth table". A truth table lists all possible combinations of inputs and the corresponding outputs. 2

3. Basic Gates NOT GATE (INVERTER) It is a gate with only 1 input and a complemented output. 3

4. Basic Gates AND GATE This is a gate with 2 or more inputs. The output is HIGH only when all inputs are HIGH. 4

5. Basic Gates OR GATE This is a gate with 2 or more inputs. The output is HIGH when any input is HIGH. 5

6. Universal Gates NOR GATE This represents an OR gate followed by an inverter. 6

7. Universality of NOR Gate 7

8. Universal Gates NAND GATE This represents an AND gate followed by an inverter. 8

9. Universality of NAND Gate 9

10. EXCLUSIVE-OR GATES The exclusive-OR gate has a high output only when an odd number of inputs is high. OR Y = A ⨁ B 10

11. EXCLUSIVE-OR GATES 11

12. EXCLUSIVE-NOR GATES EX-NOR Gate Truth Table Y = A ⨀ B OR or   12 A B Y 1 1 1 1 1 1 Y B A

13. Introduction Each gate input is labelled with a variable . Each appearance of a variable or its complement in an expression will be referred to as a literal. The following expression, which has three variables, has 10 literals ab′c + a′b + a′bc ′ + b′c ′ A truth table (also called a table of combinations) specifies the values of a Boolean expression for every possible combination of values of the variables in the expression. 13

14. Introduction An expression is said to be in sum-of-products (SOP) form when all products are the products of single variables. E.g. AB′ + CD′E + AC′E′ A sum-of-products expression can be realized using one or more AND gates feeding a single OR gate at the circuit output. An expression is in product-of-sums (POS) form when all sums are the sums of single variables. E.g. (A + B′)(C + D′ + E)(A + C′ + E′) A product-of-sums expression can be realized using one or more OR gates feeding a single AND gate at the circuit output. 14

15. Introduction 15

16. Introduction Redundant Terms: The Term not or no longer needed or useful. (A + BC)(A + D + E) = A + AD + AE + ABC + BCD + BCE = A(1 + D + E + BC) + BCD + BCE = A + BCD + BCE 16

17. SUM-Of-PRODUCTS (SOP) Possible ways to AND two or more input signals that are in complement and uncomplement form. A SOP expression is two or more AND functions ORed together. Example: 17 XY + X′Z + YZ

18. SUM-Of-PRODUCTS (SOP) 18 ANDing two variables and their complements

19. SUM-Of-PRODUCTS (SOP) The fundamental products are also called minterms . Products are represented by m0, m1, m2 and m3 respectively. The suffix i of mi comes from decimal equivalent of binary values that makes corresponding product term high.   19

20. SUM-Of-PRODUCTS (SOP) Example: Fundamental Products for Three Inputs 20

21. SUM-Of-PRODUCTS (SOP) The above three variable minterms can alternatively be represented by mo , m1, m2, m3, m4, m5, m6, and m7 respectively. Note that, for n variable problem there can be 2 n number of minterms . The fundamental products by listing each one next to the input condition that results in a high output. For instance, when A = 1, B = 0 and C = 0, the fundamental product results in an output of 21

22. Sum-of-Products Equation Sum-of-Products Equation The Sum-of-products solution, for given a truth table shown below. Write down the fundamental product for each output 1 in the truth table. For example, the first output 1 appears for an input of A = 0, B = 1, and C = 1. The corresponding fundamental product is .   22

23. Sum-of-Products Equation To get the sum-of-products equation, all you have to do is OR the fundamental products Alternate representation 23

24. Sum-of-Products Equation-3 where '∑:' symbolizes summation or logical OR operation that is performed on corresponding minterm’s and Y = F (A, B, C) means Y is a function of three Boolean variables A, B and C. This kind of representation of a truth table is also known as canonical sum form. 24

25. Logic Circuit 25

26. PRODUCT-Of-SUMS METHOD Given a truth table, identify the fundamental sums needed for a logic design. Then by ANDing these sums, will get the product-of-sums equation corresponding to the truth table. But, in the sum-of-products method, the fundamental product produces an output l for the corresponding input condition. But with the product of- sums method, the fundamental sum produces an output 0 for the corresponding input condition. 26

27. PRODUCT-Of-SUMS METHOD-2 Converting a Truth Table to an Equation 27

28. PRODUCT-Of-SUMS METHOD-3 Logic Circuit 28

29. PRODUCT-Of-SUMS METHOD-4 Conversion between SOP and POS SOP and POS occupy complementary locations in a truth table. Identifying complementary locations, Changing minterm to maxterm or reverse, and Changing summation by product or reverse. 29

30. DON'T-CARE CONDITIONS 30 In digital systems, certain input conditions never occur during normal operation; therefore, the corresponding output never appears. Since the output never appears, it is indicated by an X in the truth table. The X is called a don 't-care condition. Whenever you see an X in a truth table, you can let it equal either 0 or 1, whichever produces a simpler logic circuit.

31. DON'T-CARE CONDITIONS Truth Table with Don’t-Cares In Minterm form F =Σ m(0, 3, 7) +Σ d(1, 6) In Maxterm form F =Π M(2, 4, 5)· Π D(1, 6) 31

32. DON'T-CARE CONDITIONS Truth Table with Don't-Care Conditions Y=F(A,B,C,D) = ∑m (9) + d(10,11,12,13,14,15) 32

33. Karnaugh Maps Switching functions can generally be simplified by using the algebraic techniques. However, two problems arise when algebraic procedures are used: 1. The procedures are difficult to apply in a systematic way. 2. It is difficult to tell when you have arrived at a minimum solution. The Karnaugh map method and the Quine- McCluskey procedure used to overcome these difficulties by providing systematic methods for simplifying switching functions. The Karnaugh map is useful tool for simplifying and manipulating switching functions of three or four variables (Literals). 33

34. 12/14/2023 34 Karnaugh Maps TwoVariable Karnaugh Maps

35. 12/14/2023 35 Three-Variable Karnaugh Maps Karnaugh Maps

36. 12/14/2023 36 Four-Variable Karnaugh Maps Karnaugh Maps

37. 12/14/2023 37 Two Variable K-MAP

38. 12/14/2023 38 Three Variable K-MAP

39. 12/14/2023 39 FOUR Variable K-MAP

40. 12/14/2023 40 K-MAP for given truth table Y=A’B’+A’B

41. 12/14/2023 41 K-MAP for given truth table Y=A’BC’+ABC’+ABC

42. 12/14/2023 42 K-MAP for given truth table Y=A’B’C’D+A’BCD+A’BCD’+ABCD’

43. 12/14/2023 43 K-MAP Grouping Pairs

44. 12/14/2023 44 K-MAP Grouping Pairs

45. 12/14/2023 45 K-MAP Grouping QUAD

46. 12/14/2023 46 K-MAP Grouping QUAD

47. 12/14/2023 47 K-MAP Grouping OCtETS

48. 12/14/2023 48 K-MAP Grouping Symmetric

49. 12/14/2023 49 Problems on K-map

50. 12/14/2023 50 Problems on K-map

51. 12/14/2023 51 Problems on K-map

52. 12/14/2023 52 Problems on K-map

53. 53 Problems on K-map

54. 54 Problems on K-map

55. Problems on K-map with DON'T-CARE CONDITIONS Truth Table with Don’t-Cares In Minterm form F =Σ m(0, 3, 7) +Σ d(1, 6) In Maxterm form F =Π M(2, 4, 5)· Π D(1, 6) 55

56. 12/14/2023 56 Problems on K-map with DON'T-CARE CONDITIONS

57. F(A,B,C,D)= Σ m(1,5,6,12,13,14) +Σ d(4) 12/14/2023 57 Problems on K-map with DON'T-CARE CONDITIONS PI= BC’,BD’,A’C’D Y= BC’+BD’+A’C’D

58. 12/14/2023 58 Problems on K-map with DON'T-CARE CONDITIONS

59. 12/14/2023 59 Problems on K-map with DON'T-CARE CONDITIONS

60. 12/14/2023 60 Problems on K-map with DON'T-CARE CONDITIONS

61. 12/14/2023 61 Problems on K-map with DON'T-CARE CONDITIONS

62. 12/14/2023 62 Problems on K-map with DON'T-CARE CONDITIONS

63. 12/14/2023 63 Problems on K-map with DON'T-CARE CONDITIONS

64. 12/14/2023 64 Problems on K-map

65. 12/14/2023 65 Problems on K-map

66. 12/14/2023 66 Problems on K-map

67. 12/14/2023 67 Problems on K-map

68. 12/14/2023 68 Problems on K-map

69. 12/14/2023 69 Problems on K-map

70. 12/14/2023 70 Problems on K-map

71. 12/14/2023 71 Problems on K-map

72. 12/14/2023 72 Problems on K-map

73. Determination of Minimum Expressions Using Essential Prime Implicants 73

74. QUINE- McCLUSKY METHOD Drawbacks of K Map method Karnaugh map method is very simple and intuitively appealing is somewhat subjective. It depends on the user's ability to identify patterns that gives largest size. Also the method becomes difficult to adapt for simplification of 5 or more variables. QM method is Tabular Method of Minimisation Quine-McClusky method involves preparation of two tables; one determines prime implicants and the other selects essential prime implicants to get minimal expression. 74

75. QUINE- McCLUSKY METHOD The Quine- McCluskey method reduces the minterm expansion (standard sumof -products form) of a function to obtain a minimum sum of products. The procedure consists of two main steps: Eliminate as many literals as possible from each term by systematically applying the theorem XY + XY′ = X. The resulting terms are called prime implicants . Use a prime implicant chart to select a minimum set of prime implicants which, when ORed together, are equal to the function being simplified and which contain a minimum number of literals. 75

76. F(A,B,C) =Σ m(0, 1, 2, 5, 6, 7) 12/14/2023 76 Quine-McClusky Method

77. QUINE- McCLUSKY METHOD 77

78. 12/14/2023 78 QUINE- McCLUSKY METHOD- Finding essential Prime Implicants

79. 12/14/2023 79 QUINE- McCLUSKY METHOD

80. 12/14/2023 80 QUINE- McCLUSKY

81. 12/14/2023 81 QUINE- McCLUSKY METHOD- Finding essential Prime Implicants

82. 12/14/2023 82 QUINE- McCLUSKY METHOD

83. 12/14/2023 83 QUINE- McCLUSKY METHOD- Finding essential Prime Implicants

84. 12/14/2023 84 QUINE- McCLUSKY METHOD

85. 12/14/2023 85 QUINE- McCLUSKY METHOD- Finding essential Prime Implicants

86. 12/14/2023 86

87. 12/14/2023 87

88. 12/14/2023 88 QUINE- McCLUSKY METHOD

89. 12/14/2023 89 QUINE- McCLUSKY METHOD F(A,B,C) = ∏ M (0, 5,6,7,8,9,13,15)

90. 12/14/2023 90 QUINE- McCLUSKY METHOD

91. 12/14/2023 91 QUINE- McCLUSKY METHOD

92. 12/14/2023 92 NAND – NAND Realization Convert the following circuit using NAND gates only.

93. 12/14/2023 93 NAND – NAND Realization

94. 12/14/2023 94 NAND – NAND Realization

95. 12/14/2023 95 NAND – NAND Realization

96. 12/14/2023 96 NOR – NOR Realization Convert the following circuit using NAND gates only.

97. 12/14/2023 97 NOR – NOR Realization

98. 12/14/2023 98 NOR – NOR Realization

99. Hardware Description Language In  computer engineering , a  hardware description language  ( HDL ) is a specialized  computer language  used to describe the structure and behavior of  electronic circuits , and most commonly,  digital logic  circuits. There are two major hardware description languages:  VHDL  and  Verilog . 12/14/2023 99

100. VHDL The Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is a language that describes the behavior of electronic circuits, most commonly digital circuits. There are different types of description in them: "dataflow, behavioral and structural". 12/14/2023 100 Hardware Description Language

101. Structure of VHDL Program Structure of VHDL Program Every VHDL program consists of at least one entity/architecture pair. In a large design, you will typically write many entity/architecture pairs and connect them together to form a complete circuit. An entity declaration describes the circuit as it appears from the “outside” - from the perspective of its input and output interfaces. The second part of a minimal VHDL design description is the architecture declaration. ENTITY: ENTITY is the list with specifications of all input and output pins of the circuit. Its syntax is shown below : ENTITY name IS PORT ( port_name : signal_mode signal_type ; port_name : signal_mode signal_type ; ... ); END name;  The mode of the signal used may be IN, OUT, INOUT or BUFFER. IN and OUT are unidirectional pins, while INOUT is bidirectional. BUFFER, is used when the output signal is used internally in the design. The type of the signal may be BIT, STD_LOGIC, INTEGER, etc. The name of the entity should be not use the VHDL reserved words. 12/14/2023 101

102. ARCHITECTURE: The ARCHITECTURE is the description of how the circuit of design works. Its syntax is as follows, ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name ;  12/14/2023 102 Structure of VHDL Program