monolithic integrated 3d circuits technology

trends and futures

1. DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Technical Seminar Topic : Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects Presented By Kushal Kumar R 4VM21EC042 Under the guidance of Prof. Lalitha N Department of ECE VVIET

2. Dept. of E&C Engg., VVIET, Mysuru 2 Introduction Technology Application Conclusion References Contents

3. Dept. of E&C Engg., VVIET, Mysuru 3 Introduction Monolithic 3D IC (Integrated Circuit) design is an advanced technology that extends the capabilities of traditional 2D ICs by stacking multiple layers of devices vertically on a single chip. This approach offers several advantages, including improved performance, reduced power consumption, and smaller footprint. In monolithic 3D ICs, devices are fabricated sequentially, one layer on top of another, with nanoscale inter-tier vias (MIVs) providing connections between the layers.

4. Dept. of E&C Engg., VVIET, Mysuru 4 Introduction This method eliminates the need for aligning tiers, as seen in other 3D integration technologies like through-silicon vias (TSVs), and allows for higher integration density and increased vertical connectivity. There are three main types of monolithic 3D IC implementations: Transistor-level : NMOS and PMOS transistors are partitioned into separate tiers with MIVs for intra-cell and inter-cell connections. Gate-level : Cells are split into two tiers, with MIVs used only for inter-cell connections. Block-level : Higher-level functional blocks are floor planned into separate tiers, with MIVs providing the necessary connections.

5. Dept. of E&C Engg., VVIET, Mysuru 5 . Monolithic 3D IC design involves several advanced technologies that enable the stacking of multiple layers of devices on a single chip. Here are some key technologies involved: Monolithic Inter-tier Vias (MIVs) : These nanoscale vias connect the different layers of devices, providing high vertical integration density and lower resistive-capacitive (RC) parasitic compared to through-silicon vias (TSVs). Low-Temperature Processing : To fabricate the top-tier devices without damaging the bottom-tier devices, low-temperature processes are used. This includes low-temperature deposition and annealing techniques. Recessed Channel Transistors (RCATs) : These transistors are formed using etch and deposition tools, allowing for the creation of transistors on the top structure of the chip. Oxide-to-Oxide Bonding : This process involves bonding a donor wafer on top of the original CMOS processed wafer using an oxide layer, followed by cleaving or indenting the top structure Technology

6. Dept. of E&C Engg., VVIET, Mysuru 6 . Technology Monolithic Inter-tier Vias (MIVs): Monolithic Inter-tier Vias (MIVs) are a crucial component in monolithic 3D IC design, enabling the vertical integration of multiple device layers on a single chip. What are MIVs? MIVs are nanoscale vias that connect different layers of devices in a monolithic 3D IC. They are significantly smaller than traditional through-silicon vias (TSVs), allowing for higher integration density and improved performance.

7. Dept. of E&C Engg., VVIET, Mysuru 7 . Technology Key Features of MIVs: Size and Density : MIVs are extremely small, with diameters typically less than 100 nm . This small size allows for a high density of vertical connections, which is essential for achieving the benefits of monolithic 3D ICs. Low RC Parasitic : Due to their small size, MIVs have lower resistive-capacitive (RC) parasitic compared to TSVs . This results in faster signal propagation and reduced power consumption. Sequential Integration : MIVs are created through a sequential integration process, where each layer of devices is fabricated one on top of another . This eliminates the need for die alignment, further reducing the size and complexity of the vias.

8. Dept. of E&C Engg., VVIET, Mysuru 8 . Technology Fabrication Process: Oxide-to-Oxide Bonding : Oxide-to-oxide bonding is a key technique used in semiconductor and MEMS (Micro-Electro-Mechanical Systems) fabrication to create strong, reliable bonds between two oxidized surfaces, typically silicon dioxide ( SiO ₂). This method is essential for wafer-level packaging, 3D integration, and hermetic sealing in advanced microelectronics. The most commonly used materials are: Silicon oxynitride ( SiON ) , Aluminum oxide ( Al₂O ₃) , Tantalum pentoxide ( Ta₂O ₅) Surface Preparation Surface Activation Bonding Process Annealing

9. Dept. of E&C Engg., VVIET, Mysuru 9 . Technology Surface Preparation : The bonding surfaces, typically silicon dioxide ( SiO ₂), are cleaned and polished to achieve ultra-smooth and contaminant-free surfaces. Chemical Mechanical Polishing (CMP) is often used. Surface Activation : Plasma treatment or chemical activation is applied to make the surfaces hydrophilic, enhancing their bonding capability. Bonding Process : The activated surfaces are brought into contact under controlled conditions. This can be done at room temperature or with slight heating to improve adhesion. Annealing : The bonded wafers are subjected to thermal annealing to strengthen the bond. This step facilitates the formation of covalent bonds between the oxide layers.

10. Dept. of E&C Engg., VVIET, Mysuru 10 . Technology 2.Low-Temperature Processing : To avoid damaging the bottom-tier devices, low-temperature deposition and annealing techniques are used to fabricate the top-tier devices . Low Temperature Processing Chemical Vapor Deposition (CVD) Plasma-Enhanced CVD Low-Temperature Annealing Low-Temperature Oxidation

11. Dept. of E&C Engg., VVIET, Mysuru 11 Low-Temperature Chemical Vapor Deposition (CVD) : Used for depositing thin films like silicon nitride or silicon dioxide at temperatures below 800°C. This minimizes dopant diffusion and stress on the substrate. Plasma-Enhanced CVD (PECVD) : A variant of CVD that uses plasma to enhance chemical reactions, allowing deposition at even lower temperatures, typically around 300–400°C. Low-Temperature Annealing : Techniques like rapid thermal annealing (RTA) or laser annealing are employed to activate dopants or repair defects without exposing the wafer to prolonged high temperatures. Low-Temperature Oxidation : Achieved using techniques like plasma oxidation or ozone-based oxidation, which form high-quality oxide layers at reduced temperatures. Technology

12. Dept. of E&C Engg., VVIET, Mysuru 12 Mobile Devices : Monolithic 3D ICs are ideal for mobile System-on-Chip (SoC) applications, where space is limited, and high performance is required. High-Performance Computing (HPC) : In HPC systems, Monolithic 3D ICs can significantly enhance performance by reducing interconnect delays and increasing bandwidth. High-Performance Computing (HPC) : In HPC systems, Monolithic 3D ICs can significantly enhance performance by reducing interconnect delays and increasing bandwidth. Data Centers : Data centers benefit from Monolithic 3D ICs by achieving higher processing power and energy efficiency. Consumer Electronics : Devices like smartphones, tablets, and wearables can leverage Monolithic 3D ICs to offer more features and better performance while maintaining a compact form factor. Applications

13. Dept. of E&C Engg., VVIET, Mysuru 13 Applications in AI and High-Performance Computing Applications 1 2 3 Accelerators GPUs, FPGAs, and custom ASICs for machine learning benefit significantly from monolithic 3D integration . Memory Stacking High-bandwidth memory (HBM) integration with logic reduces latency and increases memory bandwidth. Interposer-less Designs Reducing latency and power consumption is achieved through interposer-less designs, streamlining the 3D architecture .

14. Conclusion Dept. of E&C Engg., VVIET, Mysuru 14 In this brief presntation , the current status of MONO3D technology is presented with emphasis on fabrication. The primary process challenges related to thermal budget constraint, high quality silicon growth, and contamination are discussed, including existing approaches to these issues. At the design-level, important results on design automation, thermal integrity, and design for-test are provided with emphasis on unique MONO3D characteristics. Three specific applications that can potentially benefit from MONO3D technology are also presented.

15. Dept. of E&C Engg., VVIET, Mysuru 15 . Technology

16. References [1] “ International roadmap for devices and systems.” [Online]. Available: https://irds.ieee.org. [2] C. Lee, C. Hung, C. Cheung, P. Yang, C. Kao, D. Chen, M. Shih, C. C. Chien, Y. Hsiao, L. Chen, M. Su, M. Alfano, J. Siegel, J. Din, and B. Black, “An overview of the development of a gpu with integrated hbm on silicon interposer,” in IEEE Electronic Components and Technology Conference, pp. 1439–1444. [3] “Nvidia tesla p100,” https://www.nvidia.com/en-us/data-center/teslap100/. [4] T. Pawlowski, “Hybrid memory cube ( hmc ),” in Proceedings of the IEEE Hot Chips Symposium, August 2023. [5] S. M. Satheesh and E. Salman, “Power distribution in TSV-based 3D processor-memory stacks,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp. 692–703, Dec. 2021. [6] P. Shukla, S. S. Nemtzow , V. F. Pavlidis , E. Salman, and A. K. Coskun, “Temperature aware optimization of monolithic 3D deep neural network accelerators,” in ACM Asia and South Pacific Design Automation Conference, to be published, 2021. [7] E. J. Marinissen , T. McLaurin, and Hailong Jiao, “IEEE Std P1838: DfT standard-under development for 2.5D-, 3D-, and 5.5D-SICs,” in IEEE European Test Symposium, 2016, pp. 1–10. [8] “Nvidia tesla p100,” https://www.nvidia.com/en-us/data-center/teslap100/.

17. References [9] D. B. Bartolini, P. Miedl , and L. Thiele, “On the capacity of thermal covert channels in multicores,” Proceedings of the European Conference on Computer Systems, 2019. [10] “Nvidia tesla p100,” https://www.nvidia.com/en-us/data-center/teslap100/. [11] K. Chang, A. Koneru, K. Chakrabarty, and S. K. Lim, “Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper),” in IEEE/ACM International Conference on Computer-Aided Design, 2021, pp. 805–810. [12] E. J. Marinissen , T. McLaurin, and Hailong Jiao, “IEEE Std P1838: DfT standard-under development for 2.5D-, 3D-, and 5.5D-SICs,” in IEEE European Test Symposium, 2018, pp. 1–10. [13] S. K. Samal et al., “Full chip impact study of power delivery network designs in monolithic 3D ICs,” in IEEE/ACM Proc. of International Conference on Computer-Aided Design, 2024, pp. 565–572. [14] https://youtu.be/lQHNducx3do?si=oH0l1GVP29l7_9fM [15]T. Pawlowski, “Hybrid memory cube ( hmc ),” in Proceedings of the IEEE Hot Chips Symposium, August 2023

18. Dept. of E&C Engg., VVIET, Mysuru 18 THANK YOU