My lecture 18 of mpi that is of direct memory access

Direct Memory Access (DMA) is a technique used in computer systems that allows peripheral devices—such as hard drives, network cards, or sound cards—to transfer data directly to and from the main memory without continuous involvement of the central processing unit (CPU). This mechanism significantly enhances system performance and efficiency by freeing the CPU from managing data movement tasks, allowing it to focus on executing other instructions. DMA operates through a dedicated controller, known as the DMA controller, which handles the data transfer process by temporarily taking control of the system bus. When a peripheral requests a data transfer, the DMA controller manages the address and control signals, ensuring that data is moved between memory and the device efficiently. Once the transfer is complete, it signals the CPU through an interrupt. This method is especially valuable in systems requiring high-speed data transfers, such as multimedia processing and real-time applications. Overall, DMA improves throughput, reduces latency, and optimizes CPU utilization, making it a fundamental feature in modern computer architecture.

1. Direct memory access Course Code: CS-430 Course Title: Microprocessor Programming and Interfacing Prepared By: DR. Syed Aqeel Haider

2. To be covered What is DMA (Direct Memory Access) Basic DMA Operation 8237 Programmable DMA Controller

3. DIRECT MEMORY ACCESS The DMA I/O technique provides direct access to the memory while the microprocessor is temporarily disabled. This allows data to be transferred between memory and the I/O device at a rate that is limited only by the speed of the memory components in the system or the DMA controller. DMA transfers are used for many purposes, but more common are DRAM refresh, video displays for refreshing the screen, and disk memory system reads and writes. The DMA transfer is also used to do high-speed memory-to-memory transfers.

4. Basic dma operation As the timing diagram indicates, HOLD is sampled in the middle of any clocking cycle. Thus, the hold can take effect any time during the operation of any instruction in the microprocessor’s instruction set. As soon as the microprocessor recognizes the hold, it stops executing software and enters hold cycles. The HLDA signal becomes active to indicate that the microprocessor has indeed placed its buses at their high-impedance state, as can be seen in the timing diagram.

5. HOLD VS INTR & RESET HOLD input has a higher priority than the INTR or NMI interrupt inputs. Hardware Interrupts take effect at the end of an instruction, whereas a HOLD takes effect in the middle of an instruction. The only microprocessor pin that has a higher priority than a HOLD is the RESET pin.

6. 8237 Programmable dma controller Available in 40-pin DIP A3 – A0 …………………………… 4 A7 – A4 …………………………... 4 DB7 – DB0 ………………………. 8 DREQ3 – DREQ0 ……………... 4 DACK3 – DACK0 ………………. 4 HRQ , HLDA …………………….. 2 MEMR , MEMW ……….……… 2 IOR , IOW ……………..…………. 2 READY , RESET ……………..….. 2 ADSTB , AEN ……………………. 2 CS , CLK ………………………..…. 2 EOP …………………………………. 1 NC …………………………………... 1 Vcc , GND ………………………… 2

7. Microprocessor interface

8. DMA INTERFACE

9. 8237 Internal registers with offset addresses REGISTER – WRITE/READ CH0 CH1 CH2 CH3 BASE ADDRESS REGISTER (BAR) – W 2 4 6 BASE WORD COUNT REGISTER (BWCR) – W 1 3 5 7 CURRENT ADDRESS REGISTER (CAR) – R 2 4 6 CURRENT WORD COUNT REGISTER (CWCR) – R 1 3 5 7 COMMAND REGISTER – W 8 ALL CHANNELS STATUS REGISTER – R 8 ALL CHANNELS REQUEST REGISTER – W 9 ALL CHANNELS MASK REGISTER (1 - CHANNEL) – W A ALL CHANNELS MODE REGISTER – W B ALL CHANNELS TEMPORARY REGISTER – R B ALL CHANNELS CLEAR INTERNAL FLIP FLOP – W C ALL CHANNELS MASTER CLEAR – W D ALL CHANNELS CLEAR MASK REGISTER – W E ALL CHANNELS MASK REGISTER (4 – CHANNEL) – W F ALL CHANNELS

10. Channel programming example Q. Base address for 8237 DMA Controller is 80h. Channel 1 has an input device, memory block starting from address 43C0h is assigned to the channel. 4050h bytes are to be inputted and stored in memory. Write the instructions to load BAR and BWCR for channel 1. Solution: BAR: MOV AL , 0C0h ; Internal FF = 0 OUT 80h+2 , AL ; LSB of BAR loaded , Internal FF = 1 MOV AL , 43h OUT 80h+2 , AL ; MSB of BAR loaded , Internal FF = 0 BWCR: MOV AL , 50h OUT 80h+3 , AL ; LSB of BWCR loaded , Internal FF =1 MOV AL , 40h OUT 80h+3 , AL ; MSB of BWCR loaded , Internal FF =0 BAR=43C0 4050 MOV AL , 4Fh BAR  CAR BWCR  CWCR CAR  CAR + 1 CWCR  CWCR – 1 CWCR = 0000 – 1 CWCR = FFFFh (Terminal Count)

11. READING CAR & CWCR FOR CHANNEL # 2 CAR: Internal FF = 0 IN AL , 80h+4 ; LSB of CAR is read , Internal FF = 1 MOV DL , AL ; LSB moved to DL IN AL , 80h+4 ; MSB of CAR is read , Internal FF = 0 MOV DH , AL ; MSB moved to DH , (DX) = CAR for channel 2 CWCR: Internal FF = 0 IN AL , 80h+5 ; LSB of CWCR is read , Internal FF = 1 MOV CL , AL ; LSB moved to CL IN AL , 80h+5 ; MSB of CWCR is read , Internal FF = 0 MOV CH , AL ; MSB moved to CH , (CX) = CWCR for channel 2

12. 8237 Internal registers with offset addresses REGISTER – WRITE/READ CH0 CH1 CH2 CH3 BASE ADDRESS REGISTER (BAR) – W 2 4 6 BASE WORD COUNT REGISTER (BWCR) – W 1 3 5 7 CURRENT ADDRESS REGISTER (CAR) – R 2 4 6 CURRENT WORD COUNT REGISTER (CWCR) – R 1 3 5 7 COMMAND REGISTER – W 8 ALL CHANNELS STATUS REGISTER – R 8 ALL CHANNELS REQUEST REGISTER – W 9 ALL CHANNELS MASK REGISTER (1 - CHANNEL) – W A ALL CHANNELS MODE REGISTER – W B ALL CHANNELS TEMPORARY REGISTER – R B ALL CHANNELS CLEAR INTERNAL FLIP FLOP – W C ALL CHANNELS MASTER CLEAR – W D ALL CHANNELS CLEAR MASK REGISTER – W E ALL CHANNELS MASK REGISTER (4 – CHANNEL) – W F ALL CHANNELS

13. COMMAND REGISTER Q: 8237 DMA Controller’s command register is to be programmed for the following: Controller is enabled Memory to memory disabled DREQ pins are active high DACK pins are active high Rotating priority is to be used Normal timing is to be used Solution: Command Byte: 1 0 * 1 0 0 * 0 = 10010000 MOV AL , 10010000b OUT 80h+8 , AL Q: 8237 DMA Controller’s command register is to be programmed for memory to memory DMA transfer: Solution: Command Byte: * * * * * 0 0 1 = 00000001 MOV AL , 00000001b OUT 80h+8 , AL BAR = Source Memory BAR 1 = Destination Memory BWCR 1 = No. of bytes DMA Request for CH#0 Block Transfer is used

14. MODE REGISTER Q: Write mode word for programming channel#3 for the following condition: Input device is connected at channel 3 Auto-initialization is enabled Address increment is selected Transfers data in Demand Mode Solution: Mode word: 0 0 0 1 0 1 1 1 MOV AL , 00010111b OUT 80h+Bh , AL Q: Write mode word for programming channel#0 for the following condition: Output device is connected at channel 0 Auto-initialization is disabled Address decrement is selected Transfers data in Single Mode Solution: Mode word: 0 1 1 0 1 0 0 0 MOV AL , 01101000b OUT 80h+Bh , AL

15. MODE REGISTER Q: Write mode word for programming channel#2 for the following condition: Input device is connected at channel 2 Auto-initialization is disabled Address increment is selected Transfers data in Block Mode Solution: Mode word: 1 0 0 0 0 1 1 0 MOV AL , 10000110b OUT 80h+Bh , AL Q: Write mode word for programming channel#1 for the following condition: 8237 DMAC is connected at channel 1 Transfers data in Cascade Mode Solution: Mode word: 1 1 * * * * 0 1 MOV AL , 11000001b OUT 80h+Bh , AL

16. REQUEST REGISTER & MASK REGISTER (1-CHANNEL) Q: Write the instructions to initiate memory to memory DMA transfer and to read temporary register: Solution: Request Register: * * * * * 1 0 0 = 00000100 MOV AL , 00000100b OUT 80h+9 , AL ; memory to memory initiated IN AL , 80h+Bh ; Temporary register is read Q: Write the instructions to disable channel # 1 of DMA Controller: Solution: Mask Register: * * * * * 1 0 1 = 00000101 MOV AL , 00000101b OUT 80h+Ah , AL

17. MASK REGISTER (4-CHANNEL) & STATUS REGISTER Q: Write the instructions to disable channel # 1 and 3 of DMA Controller: Solution: Mask Register: * * * * 1 0 1 0 = 00001010 MOV AL , 00001010b OUT 80h+Fh , AL Q: Write the instructions to read the status register for DMA Controller: Solution: IN AL , 80h+8h ; Status is read If (AL) = 0 1 1 0 1 0 0 0 , then Channels # 1 & 2 are having active interrupt requests and Channel # 3 has just reached terminal count

18. CLEAR INTERNAL FLIP FLOP & MASTER CLEAR & CLEAR MASK REGISTER CLEAR INTERNAL FLOP FLOP : OUT 80h+Ch , AL MASTER CLEAR: OUT 80h+Dh , AL CLEAR MASK REGISTER: OUT 80h+Eh , AL

19. thank you