Paging using tlb in operating System.pptx

Paging using translation lookaside buffer

1. HARDWARE SUPPORT

2. Translation Lookaside Buffer (TLB) in Paging : A Translation look aside buffer can be defined as a memory cache which can be used to reduce the time taken to access the page table again and again.
It is a memory cache which is closer to the CPU and the time taken by CPU to access TLB is lesser then that taken to access main memory. In other words, we can say that TLB is faster and smaller than the main memory but cheaper and bigger than the register.

3. Conditions of TLB : TLB hit is a condition where the desired entry is found in translation look aside buffer. If this happens then the CPU simply access the actual location in the main memory.
However, if the entry is not found in TLB (TLB miss) then CPU has to access page table in the main memory and then access the actual frame in the main memory.
Therefore, in the case of TLB hit, the effective access time will be lesser as compare to the case of TLB miss.

4. ARCHITECTURE

5. Steps in TLB hit CPU generates a virtual (logical) address. It is checked in TLB (present). The corresponding frame number is retrieved, which now tells where the main memory page lies.

6. Steps in TLB miss : CPU generates a virtual (logical) address.
It is checked in TLB (not present). Now the page number is matched to the page table residing in the main memory (assuming the page table contains all PTE).
The corresponding frame number is retrieved, which now tells where the main memory page lies.
The TLB is updated with new PTE (if space is not there, one of the replacement techniques comes into the picture i.e either FIFO, LRU or MFU etc).

7. Effective memory access time(EMAT) We can calculate the EMAT by using the formula, “EMAT=h×( c+m )+(1−h)×( c+nm )” H is the hit ratio of the TLB,
m is the memory access time,
c is the TLB access time and
n represents the system level

8. THANK YOU By     Chethanand.V (22AI007)