phase 1 211010005,211010007,211010011.pptx

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1. WELCOME Under graduation Thesis Defense EEE-400A Department of EEE, Green University of Bangladesh Fall 2023

2. Design and Implementation of Sequential Logic using Reversible Logic Gates OBYDULLAH Slide No: 02 of 14

3. 01 03 05 07 08 06 04 02 Literature Review Objective of Work Gantt Chart Reference Introduction Problem of Statement Proposed Methodology Conclusion CONTENT OBYDULLAH Slide No: 03 of 14

4. INTRODUCTION Reversible Logic Applications Types of Reversible Logic OBYDULLAH Slide No: 04 of 14 Reversible gates or reversible logic gates are the gates with a property of equal number of inputs and outputs. Quantum Computing Low-Power Computing Digital Signal Processing (DSP) Nanotechnology Cryptography Toffoli Gate Fredkin Gate Peres Gate Feynman Gate

5. LITERATURE REVIEW Author & Published Date Title of Paper Methodology Used Strength of Research Limitation IEEE-2012 Design of sequential circuit using reversible logic 0.35μm CMOS technology Negligible average power dissipation Delay time and size of transistor IEEE-2012 Design of Fault Tolearnt Full Adder/ Subtractor Using Reversible Gates Fault tolerant reversible logic gates Less garbage output Power consumption and low cost IEEE-2014 Reversible Logic Gate Implementation as Switch Controlled Reversible Full Adder/Subtractor CMOS technology Using less number of transistor Power consumption and delay time IEEE-2016 DESIGN OF BASIC SEQUENTIAL CIRCUITS USING REVERSIBLE LOGIC CMOS technology Reduction in quantum cost and garbage outputs Power consumption IEEE-2018 Reversible Logic Gates and its Performances 0.5 μm & 2 μm CMOS technology And 0.5 μm & 2 μm pass transistor technology Energy consumption and less delay May be further improvement is possible both in power and delay time IEEE-2021 Realization of testable D Flip-Flop based on reversible logic CMOS technology Circuit power dissipation decreases Delay and area efficient MD. ABU KAWSAR Slide No: 05 of 14

6. OBJECTIVE OF RESEARCH 01 Power consumption is one of the vital parameters in logic circuit . As a result this research work aims to reduce power consumption Minimize The Power Consumption Rate 02 Decrease delay time in reversible logic is crucial to enhance computational speed and efficiency. Decrease The Delay Time 03 Reducing the CMOS (Complementary Metal-Oxide-Semiconductor) number in reversible logic is essential to reduce power consumption and enhance efficiency Reduce Number Of Transistors MD. ABU KAWSAR Slide No: 06 of 14

7. 01 PROBLEM STATEMENT Using Reversible Logic, The Transistor Count Is Less, Compare To Other Logic Gate. 02 Average Power Consumption Rate Is Decrease, When We Use Reversible Logic Gate. 03 Minimizing Delay Times While Using Reversible Logic Circuits While Maintaining Computational Accuracy And Efficiency . MD. ABU KAWSAR Slide No: 07 of 14

8. PROPOSED METHODOLOGY 1 6 2 5 3 4 Literature Review Comparison More study About Reversible Logic Result And Analysis Study About CMOS Technology Simulations Md. Jamil Ahmed Slide No: 08 Of 14

9. GANTT CHART MD. JAMIL AHMED Slide No: 09 of 14 Obs. Literature Review More Study About Reversible Logic Study About CMOS Technology Simulations Result And Analysis Comparison Month 1 2 3 4 5 6 7 8 9 10 11 12

10. CONCLUSION Availability Limitations Recommendations MD. JAMIL AHMED Slide No: 10 of 14 Theoretical Foundation. Electronic Design Automation Tools. Research and Development Complexity to design the circuit. Quantum Realization Limited Application Domains Practical Applications Education and Training Optimization Techniques

11. REFERENCE   [1] Ieee , 2012 International Conference on Advances in Engineering, Science and Management. IEEE, 2012. [2] IEEE Control Systems Society. Chapter Malaysia and Institute of Electrical and Electronics Engineers, 4th ICCSCE 2014 : proceedings : 4th IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014) : 28 Nov - 30 Nov 2014, Parkroyal Penang Resort, Batu Ferringhi , Penang Malaysia . [3] Institute of Electrical and Electronics Engineers. DMI College of Engineering Student Branch, Institute of Electrical and Electronics Engineers. Madras Section., and Institute of Electrical and Electronics Engineers, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016 : 3rd-5th, March 2016 . [4] JCT College of Engineering and Technology, IEEE Aerospace and Electronic Systems Society, and Institute of Electrical and Electronics Engineers, ICISC 2018 : proceedings of the 2nd International Conference on Inventive Systems and Control (ICISC 2018) : 19-20 January 2018 . [5] P. Tomar, P. P. Bansod , R. C. Gurjar, and R. Jarwal , “Realization of testable D Flip-Flop based on reversible logic,” in 2021 5th International Conference on Information Systems and Computer Networks, ISCON 2021 , Institute of Electrical and Electronics Engineers Inc., 2021. doi : 10.1109/ISCON52037.2021.9702499. [6] S. Chowdhury Kolay , S. Chattopadhyay, and M. Bandyopadhyay, “Design and Development of SS Reversible Logic Gate and it’s Application as Adder Subtractor,” in Proceedings of the 5th International Conference on Inventive Computation Technologies, ICICT 2020 , Institute of Electrical and Electronics Engineers Inc., Feb. 2020, pp. 977–981. doi : 10.1109/ICICT48043.2020.9112514. [7] P. N. Astya , Galgotias University. School of Computing Science and Engineering, Institute of Electrical and Electronics Engineers. Uttar Pradesh Section, and Institute of Electrical and Electronics Engineers, IEEE International Conference on Computing, Communication and Automation (ICCCA 2017) : proceeding : on 5th-6th May, 2017 . [8] IEEE Staff and IEEE Staff, 2012 International Conference on Computer Communication and Informatics.

12. Thanks To MD. HASAN MARUF Assistant Professor Department of EEE, Green University of Bangladesh Presented By MD. JAMIL AHMED ID 211010011 Department of EEE, Green University of Bangladesh MD. ABU KAWSAR ID 211010005 Department of EEE, Green University of Bangladesh OBYDULLAH ID 211010007 Department of EEE, Green University of Bangladesh

13. Department of Electrical and Electronic Engineering Green University of Bangladesh