Physical Design - Import Design Flow Floorplan

Physical design is process of transforming netlist into layout
which is manufacture-able [GDS]. Physical design process is
often referred as PnR (Place and Route) / APR (Automatic Place
& Route). Main steps in physical design are placement of all
logical cells, clock tree synthesis & routing. During this process
of physical design timing, power, design & technology
constraints have to be met. Further design might require being
optimized w.r.t area, power and performance.

1. PD Flow I –Floorplan

2. •Physicaldesignisprocessoftransformingnetlistintolayout
whichismanufacture-able[GDS].Physicaldesignprocessis
oftenreferredasPnR(PlaceandRoute)/APR(AutomaticPlace
&Route).Mainstepsinphysicaldesignareplacementofall
logicalcells,clocktreesynthesis&routing.Duringthisprocess
ofphysicaldesigntiming,power,design&technology
constraintshavetobemet.Furtherdesignmightrequirebeing
optimizedw.r.tarea,powerandperformance.
•

3. General Physical Design Flow is shown
below,

4. 1. IMPORT DESIGN / NETLISTIN
•ImportdesignisthefirststepinPhysicalDesign.Inthisstageallrequired
inputs&requiredreferencesarereadintothetool.Andalsobasicchecks
aredone(design,technologyconsistency).
Inputsrequired
1.Gatelevelnetlist
2.Logical(Timing)&Physicalviewsofstandardcells&allotherIPsusedin
thedesign
3.Timingconstraints(SDC)
4.PowerIntent(UPF/CPF)
5.FPDEF&ScanDEF
6.Technologyfile
7.RCCo-efficientfiles

5. How to qualify Import Design?
Checkerrors&warningwhilereadingnetlist.Understandallwarnings
•Checkforuniquification&emptymodules
•Checkerrors&warningwhilereadingtimingconstraints.Understandall
warnings
•Checkerrors&warningwhilereadingUPF/CPF.Understandallwarnings
•TimingQoR(MinimalviolationswithfixableWNS&TNS)
•CheckMVDesign(EquivalenttoLPchecks).Fixallerrors&understandall
warning
•Checkforassign&tristatements(Usuallyitschecked&fixedafter
Synthesis)

6. •Timing analyses after Import Design
•Itisalwaysagoodpracticetodoquicktiminganalysesafter
importdesign.Eventhoughpostsynthesistiminganalysesisdone
intimingtool(PT,Tempus/ETS),it’sbettertocheckpost
synthesistimingQoRinPnRtoolsalso(ICC,Innovus,Olympus)
beforeactualimplementationstarts.
•Whyitisrequired?
•CC/Innovusoptimizescriticaltimingpaths(violatingpaths)
whichareseenbyit.TherecanbechancesthatPnRtoolis
showingacompletedifferenttimingQoR(hugeviolations)
comparedtoPostSynQoRseeninPT/Tempus.Itcanbebecause
ofcorrelationissue/constraintsissue.Wecanavoidunnecessary
optimization;timing&designclosurewillbeeasyifwecorrelate
ImportDesigntimingQoRwithPostSyntimingQoR.

7. FLOORPLAN
•Floorplanisonethecritical&importantstepinPhysicaldesign.
QualityofyourChip/Designimplementationdependsonhowgood
istheFloorplan.Agoodfloorplancanbemakeimplementation
process(place,cts,route&timingclosure)cakewalk.Onsimilar
linesabadfloorplancancreateallkindissuesinthedesign
(congestion,timing,noise,ir,routingissues).Abadfloorplanwill
blowupthearea,power&affectsreliability,lifeoftheICandalsoit
canincreaseoverallICcost(moreefforttoclosure,more
LVTs/ULVTs)
•BeforestaringofFloorplan,itisbettertohavebasicdesign
understanding,dataflowofthedesign,integrationguidelinesofany
specialanaloghardIPsinthedesign.Andforblock/partitionlevel
designsunderstandingtheplacement&IOinteractionsoftheblock
inFullchipwillhelpincomingupwithgoodfloorplan.

8. •What is required to come with a good floorplan?
1.Basic design understating
2.Data flow diagram (DFA / Analyzelogic connectivity in Synopsys ICC)
3.Integration guidelines
4.IO / Pin placement requirements
5.Special requirements from Full Chip floorplan
6.MV / LP requirements. Understanding of PDs & Vas
•Different types of partitions / blocks
1.Memory intensive digital cores, graphic cores
2.Partitions / Blocks with analogHard IPs
3.DDR & other High Speed Interface partitions / blocks / sub-systems
4.Channel partitions

9. •Partitions with different critical tasks
1.Timing critical
2.Routing critical / Congestion
3.Blocks with complex Clock structure
•Types of floorplan techniques used in Full Chip plan
1.Abutted (All inter block pin connections are done through FTs)
2.Non abutted (Channel based. All inter block pin connections are
routed in channels)
3.Mix of both –partially abutted with some channels

11. FLOORPLAN STEPS
•Size&shapeoftheblock(UsuallyprovidedbyFCfloorplan)
•Voltageareacreation(Powerdomains)
•IOplacement
•Creatingstandardcellrows
•Macro-placement
•Addingrouting&placementblockages(asrequired)
•Addingpowerswitches(Daisychain)
•CreatingPowerMesh
•Addingphysicalcells(Welltaps,EndCapsetc)
•Placing&qualifyingpushdowncells
•Creatingbounds/plangroups/densityscreens

12. Detailed discussion
•Inmulti-voltage&multipowerdomaindesigns,voltageareas
arerequiredtoguidethetooltounderstanddifferentdomains.
•Therearetwomethodstocreatevoltagearea;
1.Abuttedvoltagearea(Cellsarenotallowedtoplaceindefault
voltagearea)
1.Asisnodefaultdomainarea,voltageareafeed-through(VA-FT)are
requiredtocrossoverdifferentvoltageareas.
2.Non-abuttedvoltagearea(Cellsareallowedtoplaceindefault
voltagearea)

14. •1.Shape&sizeoftheblock/partition
•Inmostofthecase,blocksize&shapeisdecidedbyFCfloorplan.
Rectangle/Squareshapeisbestintermsoffloorplan&furtherdesign
closure.Butinmanycase,floorplancanbeofrectilinearshapewith
manynotches.ItisalwaysgoodpracticetodiscusswithFCfloorplan
teamforanyscopetoimproveblock/partitionlevelfloorplan.
•3.IO/Pinplacement
•IOs/Pinsareplacedattheboundaryoftheblock.Usuallypinplacement
informationispusheddownfromFCfloorplan.Buttheselocationscan
bechangedbasedonblockcriticalrequirements.Anychangeinpin
locationhastobediscussedwithFCfloorplanteam.Timingcritical
interfacesneedspecialattention,likenext2-3levelsoflogicfromIOs
arepre-placedneartheIOs).Sourcesynchronousinterfacesrequires
delaybalancingtakingOCVintoconsiderations(Thiswillrequire
manualplacement&scripting)

15. •Rowsareacreatedinthedesignusingcell-site(unit/basic).Rowsaidin
systematicplacementofstandardcells.Andstandardcellpowerroutes
doneconsideringrows.
Rowscanbecut,wherevercellplacementisnotallowedORhard
placementblockagecanalsobeused.

16. •5. Macro placement
•Step 1 –Understand Pins & Orientation requirements of Macros

17. •Step 2 –Follow data flow / hierarchy to place the Macros. Make
use of reference floorplan if available

18. •Step3–AllthepinsoftheMacrosshouldpointtowardsthecore
logic
•Step4–Channelsb/wmacrosshouldbebigenoughto
accommodateallroutingreqs&shouldgetaminimumofonepair
VDD&VSSpowergridsinthechannel

19. •AutomaticFloorplan/Macro-placement
•MostofthePnRtoolsprovideautomaticfloorplanoption.
Automaticfloorplanoptioncreatesitsownmacroplacement
basedontheeffort&otheroptions.Buttheseoptionsarenot
maturedenoughtogiveoptimumfloorplanforallkindofdesigns.
Thisoptionwillbehandy,whendesignhas100sofMacros,but
generatedfloorplanneedslotofmodificationforfurther
optimizations

20. How to qualify Macro –Placement
•Allmacrosshouldbeplacedattheboundary
•Checktheorientation&pindirectionsofallmacros
•Spacingb/wmacrosshouldbeenoughforrouting&powergrid
•Macrosshouldnotblockpartitionlevelpins
•[Iterations]Lesscongestion&goodtimingQoR–Thesecannotbe
achievedinoneshot,butneedfewiterations[Thorough&deep
analysesarethekeythingswhileiterating]

21. 6. Adding placement & routing blockages
•Bufferonlyblockagesareaddedinchannelsb/wmacros.Partial
placementblockagescanbeaddedb/wthechannelsblockingsequential
cells(whoseplacementinchannelscandegradeCTSQoR).Partial
blockagesareaddedincongestionproneareas/notches/corners

22. •7. Adding power switches
•Powerswitchesarerequiredtogatethepowersupplyofgateddomain
whennotrequired.PowerswitchesareMT-CMOS(multi-threshold)
cells,whichwillhaveveryhighthresholdvoltagewhendeviceisOFF&
verylowthresholdvoltagewhendeviceison.
•Powerswitchesareinsertedinpowermesh&supplytoallgateddomain
cellswillbethroughpowerswitches.Henceasingle/fewswitchesare
notenough.Astrongnetworkofpowerswitchesconnectedindaisy
chainfashionwillbeinsertedinthedesign.

23. 8. Adding special cells (Well Taps, EndCaps, Spare Cells,
Metal ECO-able cells etc)
•Wellconnection–Almostallstandardcelllibrariesaretap-less
(substrateconnectionsarenotdone@celllevel).SoWell-tapscells
areaddedinpartition/chipleveltotiethewellstoVDD/VSS.Tap-
gatespacinghastobemetwhileaddingwell-taparray.

24. •EndCapCells–Thesecellsareinsertedtotakecareofboundary
DRCofWells&Otherlayers.EndCapCellsensureproper
terminationsofrows,sothatnoDRCarecreated.Thisisa
physical-onlycell.

25. •HowtoqualifyFloorplan?
1.CheckPGconnections(Formacros&pre-placedcellsonly)
2.LP/MVchecksonfloorplandatabase
3.CheckthepowerconnectionstoallMacros,specially
analog/specialmacrosifany
4.Allthemacrosshouldbeplacedattheboundary
5.Thereshouldnotbeanynotches/thinchannels.Ifunavoidable,
properblockageshastobeadded
6.Removeallunnecessaryplacementblockages&routing
blockages(whichmightbeputduringfloor-plan&pre-placing)
7.Checkpowerconnectiontopowerswitches
8.Checkpowermeshindifferentvoltageareavoltagearea
9.Checkpin-layers&checklayerdirections(H-V-H)