Presentation for the swing demo computer science

ssuser2a76b5 11 views 74 slides Mar 08, 2025
Slide 1
Slide 1 of 74
Slide 1
1
Slide 2
2
Slide 3
3
Slide 4
4
Slide 5
5
Slide 6
6
Slide 7
7
Slide 8
8
Slide 9
9
Slide 10
10
Slide 11
11
Slide 12
12
Slide 13
13
Slide 14
14
Slide 15
15
Slide 16
16
Slide 17
17
Slide 18
18
Slide 19
19
Slide 20
20
Slide 21
21
Slide 22
22
Slide 23
23
Slide 24
24
Slide 25
25
Slide 26
26
Slide 27
27
Slide 28
28
Slide 29
29
Slide 30
30
Slide 31
31
Slide 32
32
Slide 33
33
Slide 34
34
Slide 35
35
Slide 36
36
Slide 37
37
Slide 38
38
Slide 39
39
Slide 40
40
Slide 41
41
Slide 42
42
Slide 43
43
Slide 44
44
Slide 45
45
Slide 46
46
Slide 47
47
Slide 48
48
Slide 49
49
Slide 50
50
Slide 51
51
Slide 52
52
Slide 53
53
Slide 54
54
Slide 55
55
Slide 56
56
Slide 57
57
Slide 58
58
Slide 59
59
Slide 60
60
Slide 61
61
Slide 62
62
Slide 63
63
Slide 64
64
Slide 65
65
Slide 66
66
Slide 67
67
Slide 68
68
Slide 69
69
Slide 70
70
Slide 71
71
Slide 72
72
Slide 73
73
Slide 74
74

About This Presentation

Computer science swing demo presentations


Slide Content

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter 10Chapter 10
Input/Output OrganizationInput/Output Organization

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter OutlineChapter Outline
•Asynchronous data transfersAsynchronous data transfers
•Programmed I/OProgrammed I/O
•InterruptsInterrupts
•Direct Memory AccessDirect Memory Access
•I/O ProcessorsI/O Processors
•Serial CommunicationSerial Communication
•Serial Communication StandardsSerial Communication Standards

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Data TransfersAsynchronous Data Transfers

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data TransferSource-initiated Data Transfer

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data Destination-initiated Data
TransferTransfer

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data Transfer Source-initiated Data Transfer
with Handshakingwith Handshaking

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data Destination-initiated Data
Transfer with HandshakingTransfer with Handshaking

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Programmed I/OProgrammed I/O

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New InstructionsNew Instructions

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New Control SignalsNew Control Signals
•IO differentiates I/O and memory IO differentiates I/O and memory
accessesaccesses
–IO = 1 for I/O accessIO = 1 for I/O access
–IO = 0 for memory accessIO = 0 for memory access

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New States and RTL CodeNew States and RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU
•Modify control unit (hard-wired)Modify control unit (hard-wired)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU
•Modify control unit (hard-wired)Modify control unit (hard-wired)
•Register and ALU sections unchangedRegister and ALU sections unchanged

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU
•Modify control unit (hard-wired)Modify control unit (hard-wired)
•Register and ALU sections unchangedRegister and ALU sections unchanged
•One new micro-operation: DR One new micro-operation: DR  Input Input
PortPort

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit ChangesControl Unit Changes

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC Control Unit Changes - INC
and CLR signalsand CLR signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC Control Unit Changes - INC
and CLR signalsand CLR signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - Control Unit Changes -
Memory Read SignalMemory Read Signal
•Memory Read = READ ^ Memory Read = READ ^ IOIO’’

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
InterruptsInterrupts
•PollingPolling

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
InterruptsInterrupts
•IRQ - Interrupt RequestIRQ - Interrupt Request
•IACK - Interrupt AcknowledgeIACK - Interrupt Acknowledge

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of InterruptsTypes of Interrupts
•ExternalExternal

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of InterruptsTypes of Interrupts
•ExternalExternal
•InternalInternal

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of InterruptsTypes of Interrupts
•ExternalExternal
•InternalInternal
•SoftwareSoftware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing InterruptsProcessing Interrupts
•Do nothing (until the current instruction Do nothing (until the current instruction
has been executed)has been executed)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing InterruptsProcessing Interrupts
•Do nothing (until the current instruction Do nothing (until the current instruction
has been executed)has been executed)
•Get handler address (vectored)Get handler address (vectored)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing InterruptsProcessing Interrupts
•Do nothing (until the current instruction Do nothing (until the current instruction
has been executed)has been executed)
•Get handler address (vectored)Get handler address (vectored)
•Invoke handler routineInvoke handler routine

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Vectored Interrupt HardwareVectored Interrupt Hardware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Non-vectored Interrupt Non-vectored Interrupt
HardwareHardware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Multiple Non-vectored Multiple Non-vectored
InterruptsInterrupts

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Daisy ChainingDaisy Chaining

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
IACKIACK
inin and IACK and IACK
outout

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Parallel Priority InterruptsParallel Priority Interrupts

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Interrupt StatesInterrupt States

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Direct Memory AccessDirect Memory Access

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA ControllerDMA Controller

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer ModesDMA Transfer Modes
•Block/Burst ModeBlock/Burst Mode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer ModesDMA Transfer Modes
•Block/Burst ModeBlock/Burst Mode
•Cycle Stealing ModeCycle Stealing Mode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer ModesDMA Transfer Modes
•Block/Burst ModeBlock/Burst Mode
•Cycle Stealing ModeCycle Stealing Mode
•Transparent ModeTransparent Mode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-CPU Modifications - Micro-
operationsoperations

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-CPU Modifications - Micro-
operationsoperations

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O ProcessorsI/O Processors

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operationsI/O Processors - operations
•Block transfer commandsBlock transfer commands

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operationsI/O Processors - operations
•Block transfer commandsBlock transfer commands
•ALU operationsALU operations

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operationsI/O Processors - operations
•Block transfer commandsBlock transfer commands
•ALU operationsALU operations
•Control commandsControl commands

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit
•parity bitparity bit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit
•parity bitparity bit
•stop bit(s)stop bit(s)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit
•parity bitparity bit
•stop bit(s)stop bit(s)
•bit timebit time

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Synchronous Serial Synchronous Serial
Communication - HDLCCommunication - HDLC

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Asynchronous Universal Asynchronous
Receiver/TransmittersReceiver/Transmitters

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
UART Internal ConfigurationUART Internal Configuration

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
•Request To SendRequest To Send
•Clear To SendClear To Send
•Transmission DataTransmission Data
•Data Terminal ReadyData Terminal Ready
•Data Set ReadyData Set Ready
•Received DataReceived Data
•Data Carrier DetectData Carrier Detect
•Ring IndicatorRing Indicator
•GroundGround
RS 232C Standard - SignalsRS 232C Standard - Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active
•Use RI to indicate call statusUse RI to indicate call status

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active
•Use RI to indicate call statusUse RI to indicate call status
•Use DCD to establish connectivityUse DCD to establish connectivity

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active
•Use RI to indicate call statusUse RI to indicate call status
•Use DCD to establish connectivityUse DCD to establish connectivity
•Use TD and RD to transfer data, and Use TD and RD to transfer data, and
RTS and CTS to coordinate transfersRTS and CTS to coordinate transfers

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 422 Standard - SignalsRS 422 Standard - Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus StandardUniversal Serial Bus Standard
•Connects one port to several devicesConnects one port to several devices

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus StandardUniversal Serial Bus Standard
•Connects one port to several devicesConnects one port to several devices
•Transfers data in packetsTransfers data in packets
–Token packetsToken packets
–Data packetsData packets
–Handshake packetsHandshake packets
–Special PacketsSpecial Packets

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
USB Packet FormatsUSB Packet Formats

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
SummarySummary
•Asynchronous data transfersAsynchronous data transfers
•Programmed I/OProgrammed I/O
•InterruptsInterrupts
•Direct Memory AccessDirect Memory Access
•I/O ProcessorsI/O Processors
•Serial CommunicationSerial Communication
•Serial Communication StandardsSerial Communication Standards
Tags