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Presentation for the swing demo computer science
Presentation for the swing demo computer science
ssuser2a76b5
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Mar 08, 2025
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About This Presentation
Computer science swing demo presentations
Size:
1.45 MB
Language:
en
Added:
Mar 08, 2025
Slides:
74 pages
Slide Content
Slide 1
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter 10Chapter 10
Input/Output OrganizationInput/Output Organization
Slide 2
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter OutlineChapter Outline
•Asynchronous data transfersAsynchronous data transfers
•Programmed I/OProgrammed I/O
•InterruptsInterrupts
•Direct Memory AccessDirect Memory Access
•I/O ProcessorsI/O Processors
•Serial CommunicationSerial Communication
•Serial Communication StandardsSerial Communication Standards
Slide 3
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Data TransfersAsynchronous Data Transfers
Slide 4
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data TransferSource-initiated Data Transfer
Slide 5
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data Destination-initiated Data
TransferTransfer
Slide 6
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data Transfer Source-initiated Data Transfer
with Handshakingwith Handshaking
Slide 7
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data Destination-initiated Data
Transfer with HandshakingTransfer with Handshaking
Slide 8
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Programmed I/OProgrammed I/O
Slide 9
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample
Slide 10
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample
Slide 11
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample
Slide 12
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample
Slide 13
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
ExampleExample
Slide 14
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New InstructionsNew Instructions
Slide 15
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New Control SignalsNew Control Signals
•IO differentiates I/O and memory IO differentiates I/O and memory
accessesaccesses
–IO = 1 for I/O accessIO = 1 for I/O access
–IO = 0 for memory accessIO = 0 for memory access
Slide 16
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New States and RTL CodeNew States and RTL Code
Slide 17
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
Slide 18
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU
Slide 19
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU
•Modify control unit (hard-wired)Modify control unit (hard-wired)
Slide 20
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU
•Modify control unit (hard-wired)Modify control unit (hard-wired)
•Register and ALU sections unchangedRegister and ALU sections unchanged
Slide 21
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
•Modify register sectionModify register section
•Modify ALUModify ALU
•Modify control unit (hard-wired)Modify control unit (hard-wired)
•Register and ALU sections unchangedRegister and ALU sections unchanged
•One new micro-operation: DR One new micro-operation: DR Input Input
PortPort
Slide 22
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit ChangesControl Unit Changes
Slide 23
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC Control Unit Changes - INC
and CLR signalsand CLR signals
Slide 24
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC Control Unit Changes - INC
and CLR signalsand CLR signals
Slide 25
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - Control Unit Changes -
Memory Read SignalMemory Read Signal
•Memory Read = READ ^ Memory Read = READ ^ IOIO’’
Slide 26
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
InterruptsInterrupts
•PollingPolling
Slide 27
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
InterruptsInterrupts
•IRQ - Interrupt RequestIRQ - Interrupt Request
•IACK - Interrupt AcknowledgeIACK - Interrupt Acknowledge
Slide 28
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of InterruptsTypes of Interrupts
•ExternalExternal
Slide 29
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of InterruptsTypes of Interrupts
•ExternalExternal
•InternalInternal
Slide 30
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of InterruptsTypes of Interrupts
•ExternalExternal
•InternalInternal
•SoftwareSoftware
Slide 31
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing InterruptsProcessing Interrupts
•Do nothing (until the current instruction Do nothing (until the current instruction
has been executed)has been executed)
Slide 32
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing InterruptsProcessing Interrupts
•Do nothing (until the current instruction Do nothing (until the current instruction
has been executed)has been executed)
•Get handler address (vectored)Get handler address (vectored)
Slide 33
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing InterruptsProcessing Interrupts
•Do nothing (until the current instruction Do nothing (until the current instruction
has been executed)has been executed)
•Get handler address (vectored)Get handler address (vectored)
•Invoke handler routineInvoke handler routine
Slide 34
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Vectored Interrupt HardwareVectored Interrupt Hardware
Slide 35
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Non-vectored Interrupt Non-vectored Interrupt
HardwareHardware
Slide 36
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Multiple Non-vectored Multiple Non-vectored
InterruptsInterrupts
Slide 37
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Daisy ChainingDaisy Chaining
Slide 38
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
IACKIACK
inin and IACK and IACK
outout
Slide 39
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Parallel Priority InterruptsParallel Priority Interrupts
Slide 40
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
Slide 41
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
Slide 42
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Interrupt StatesInterrupt States
Slide 43
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Direct Memory AccessDirect Memory Access
Slide 44
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA ControllerDMA Controller
Slide 45
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer ModesDMA Transfer Modes
•Block/Burst ModeBlock/Burst Mode
Slide 46
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer ModesDMA Transfer Modes
•Block/Burst ModeBlock/Burst Mode
•Cycle Stealing ModeCycle Stealing Mode
Slide 47
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer ModesDMA Transfer Modes
•Block/Burst ModeBlock/Burst Mode
•Cycle Stealing ModeCycle Stealing Mode
•Transparent ModeTransparent Mode
Slide 48
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-CPU Modifications - Micro-
operationsoperations
Slide 49
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-CPU Modifications - Micro-
operationsoperations
Slide 50
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
Slide 51
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU ModificationsCPU Modifications
Slide 52
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O ProcessorsI/O Processors
Slide 53
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operationsI/O Processors - operations
•Block transfer commandsBlock transfer commands
Slide 54
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operationsI/O Processors - operations
•Block transfer commandsBlock transfer commands
•ALU operationsALU operations
Slide 55
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operationsI/O Processors - operations
•Block transfer commandsBlock transfer commands
•ALU operationsALU operations
•Control commandsControl commands
Slide 56
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
Slide 57
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit
Slide 58
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit
•parity bitparity bit
Slide 59
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit
•parity bitparity bit
•stop bit(s)stop bit(s)
Slide 60
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
•bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)
•start bitstart bit
•parity bitparity bit
•stop bit(s)stop bit(s)
•bit timebit time
Slide 61
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial Asynchronous Serial
CommunicationCommunication
Slide 62
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Synchronous Serial Synchronous Serial
Communication - HDLCCommunication - HDLC
Slide 63
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Asynchronous Universal Asynchronous
Receiver/TransmittersReceiver/Transmitters
Slide 64
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
UART Internal ConfigurationUART Internal Configuration
Slide 65
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
•Request To SendRequest To Send
•Clear To SendClear To Send
•Transmission DataTransmission Data
•Data Terminal ReadyData Terminal Ready
•Data Set ReadyData Set Ready
•Received DataReceived Data
•Data Carrier DetectData Carrier Detect
•Ring IndicatorRing Indicator
•GroundGround
RS 232C Standard - SignalsRS 232C Standard - Signals
Slide 66
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active
Slide 67
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active
•Use RI to indicate call statusUse RI to indicate call status
Slide 68
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active
•Use RI to indicate call statusUse RI to indicate call status
•Use DCD to establish connectivityUse DCD to establish connectivity
Slide 69
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard - RS 232C Standard -
ConnectionConnection
•Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify
that both devices are activethat both devices are active
•Use RI to indicate call statusUse RI to indicate call status
•Use DCD to establish connectivityUse DCD to establish connectivity
•Use TD and RD to transfer data, and Use TD and RD to transfer data, and
RTS and CTS to coordinate transfersRTS and CTS to coordinate transfers
Slide 70
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 422 Standard - SignalsRS 422 Standard - Signals
Slide 71
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus StandardUniversal Serial Bus Standard
•Connects one port to several devicesConnects one port to several devices
Slide 72
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus StandardUniversal Serial Bus Standard
•Connects one port to several devicesConnects one port to several devices
•Transfers data in packetsTransfers data in packets
–Token packetsToken packets
–Data packetsData packets
–Handshake packetsHandshake packets
–Special PacketsSpecial Packets
Slide 73
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
USB Packet FormatsUSB Packet Formats
Slide 74
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
SummarySummary
•Asynchronous data transfersAsynchronous data transfers
•Programmed I/OProgrammed I/O
•InterruptsInterrupts
•Direct Memory AccessDirect Memory Access
•I/O ProcessorsI/O Processors
•Serial CommunicationSerial Communication
•Serial Communication StandardsSerial Communication Standards
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