Presentation on CMOS based Domino Logic Design

Presentation on CMOS based Domino Logic Design

1. Presentation On
RECENT TRENDS IN DYNAMIC CMOS
DESIGN FOR HIGH SPEED
MICROPROCESSORS
Student Name: VIKAS MAHOR
VLSI 2010-03
Guided By : Dr.Manisha Pattanaik

ABV Indian Institute of Information Technology and Management, Gwalior, 474 010, India
28 November 2011 1

2. Introduction
Dynamic CMOS design[4]:
But aggressive scaling trends in modern day
microprocessors have reduced the effectiveness of
keeper design. This is because of process variation which
comes into picture at deep sub-100 nm technology.
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Fig 1 Dynamic
Logic CMOS
design[4]
CMOS Dynamic gates have been excellent choice in
the design of high-performance modules in modern
microprocessors.
The only limitation of dynamic gates is their relatively
low noise margin compared to that of standard CMOS
gates. Which has been resolved by employing a weak
PMOS keeper.
2

3. Introduction
Dynamic CMOS gates in High speed microprocessors:
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Fig. 2. Register files deployed in Intel’s Pentium 4
architecture[1]
Fig. 3. (a) Block diagram of a simplified register file
and (b) read port implemented
using 4 x1 multiplexer (MUX).[1]

4. Introduction contd..
Wide Fan-in dynamic OR gate:
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Fig 4 Wide Fan-in dynamic OR gate [1]
4

5. Introduction contd..
Challenges with wide fan-in OR gate design[1]:
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(a) Contention current issue in Wide Fan-in dynamic OR gates.
(b) Process variation issue at deep 100nm.
5
Wide fan-in dynamic OR gates are important structures in
microprocessors.
Contention current results in high power dissipation and delay.
Process variation results in variable leakage current through the PDN
throughout the chip. Hence we need a large keeper to maintain
appropriate noise margin.
This large keeper will in turn results in large contention current.

6. Introduction contd..
Challenges contd.. :
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Fig. 5. Dynamic OR gate with traditional keeper indicating (a) precharge phase and the evaluation phase with (b)
all input = “0” and (c) one input = “0”

7. Literature review
Wide fan-in OR gate design with delayed clock [1]:


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In this work keeper has been split into two different keepers as shown
in fig as M1 and M2. One is strong keeper and other is weak keeper.
The concept is to keep the strong keeper
OFF during the initial period of evaluation
and hence reducing the contention
current.
Reduced contention current results in
reduction in power dissipation and delay.
The drawbacks of this approach is that the
keeper is significantly weak during the
transition of the precharge/evaluation
clock signal and the complex design of the
keeper.
Fig 4 Keeper Design with
delayed clock[1]

8. Literature review contd..
Energy-Efficient Wide fan-in OR gate design [7] :
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Similar to delayed clock design here we delay the clock to the keeper.
The output node is connected to the keeper through a PMOS and a
NMOS which keeps the OFF during initial period of the evaluation phase.
Fig 5 Energy efficient
keeper design[7]
The power consumption and delay are reduced
up to a great extent.
The only disadvantage is that keeper remains
weak during the transition from precharge to
evaluation phase.

9. Literature review contd..
Variable Threshold voltage wide fan-in dynamic OR gate[1] :
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This design uses the effect of body biasing for reduction in contention
current.
Two different supply has been given to the body terminal of the keeper
VDD1 and VDD2. Where VDD2> VDD1.
During the evaluation phase VDD2 is
supplied to the M1 ensuring that
keeper should become OFF during
contention.
Drawback of this circuit is the complex
design of body bias generator.
Fig 6 Variable
threshold voltage
keeper[1]

10. Literature review contd..
programmable Wide fan-in OR gate[1] :
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This technique uses a programmable keeper so that its strength can be
adjusted using a 3-bit enable digital input.
Parameter variation is measured using a sensor and then appropriate
strength of keeper is chosen using a 3-bit
enable digital input.
 In this approach, dynamic node is
heavily loaded by gate and junction
capacitance of control and keeper
transistors, and hence, performance
can be degraded.
Fig 7 Programmable
keeper design[1]

11. Literature Review contd..
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Fig 8 Process variation tolerant keeper
design[1]
Process variation tolerant wide fan-in OR gate
design[1]:

This design uses a process variation
sensor which senses any change in
threshold voltage due to process
variation.
The variation coupled keeper than
supplies the current according to the
amount of change in threshold voltage
and keeps the noise margin at an
appropriate level.
The only disadvantage of this circuit is
the high power dissipation due to
contention current.

12. Literature Review contd..
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Comparison of Various Designs [1]:
 Figures 9(a) and 9(b) shows the comparative
analysis of various designs on the basis of delay
and power consumption with process variation
[1].

Trad. : Traditional design
Ref[1] : Process variation tolerant design
Ref[4] : programmable keeper design
Ref[6] : Keeper design with variable threshold
voltage for contention current reduction
Ref[7] : Energy-Efficient Noise-Tolerant Dynamic
Styles for scaled-Down CMOS and MTCMOS
Technologies
Ref[10]: Keeper design with delayed clock
Fig 9(a) Power and (b) Delay Comparison of
keeper designs[1]

13. Conclusion
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CMOS Dynamic gates have been excellent choice in the design of high-
performance modules in modern microprocessors.
Contention current and process variation are major bottlenecks in wide fan-in OR
gate design.
Various wide fan-in OR gate design variants have been proposed in the literature.
Some of them concentrates on process variation tolerance while some designs
reduces contention current.
Future research work will be focused on designing the a process variation tolerant
wide fan-in OR gate design with reduced contention current.

14. References
[1] Hamed F. Dadgour and Kaustav Banerjee “A Novel Variation-Tolerant Keeper Architecture
for High-Performance Low-Power Wide Fan-In Dynamic OR Gates” IEEE transaction on
VLSI systems, vol.18, NO. 11, pp. 1567 - 1577 , Nov 2010.
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[2] Rakesh Gnana David Jeyasingh, Navakanta Bhat, and Bharadwaj Amrutur, “Adaptive Keeper
Design for Dynamic Logic Circuits Using Rate Sensing Technique,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 19, no. 2, pp. 295-204,Feb. 2011.
[3] ManishaPattanaik, Fazal Rahim ,Muddala V D L Varaprasad, “Improvement of Noise Tolerance
Analysis in Deep-submicron Dynamic CMOS logic circuits”, IEEE International Conference of
Electronic Devices Systems, Page(s): 48 – 53, Year: 2010.
[4] D. Li and P. Mazumder, “On circuit techniques to improve noise immunity of CMOS dynamic logic,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 910–925, Sep. 2004.