Presentation on Counters for (Digital Systems Design).pptx

484 views 39 slides Feb 24, 2024
Slide 1
Slide 1 of 39
Slide 1
1
Slide 2
2
Slide 3
3
Slide 4
4
Slide 5
5
Slide 6
6
Slide 7
7
Slide 8
8
Slide 9
9
Slide 10
10
Slide 11
11
Slide 12
12
Slide 13
13
Slide 14
14
Slide 15
15
Slide 16
16
Slide 17
17
Slide 18
18
Slide 19
19
Slide 20
20
Slide 21
21
Slide 22
22
Slide 23
23
Slide 24
24
Slide 25
25
Slide 26
26
Slide 27
27
Slide 28
28
Slide 29
29
Slide 30
30
Slide 31
31
Slide 32
32
Slide 33
33
Slide 34
34
Slide 35
35
Slide 36
36
Slide 37
37
Slide 38
38
Slide 39
39

About This Presentation

A presentation on understanding the working of counters


Slide Content

1 COUN T ERS

Counter Counter : A sequential circuit that goes through prescribed sequence of states upon the application of clock pulse is called a counter. Th e i n pu t pu l se s a r e c al l ed c ou n t pulse s , m a y b e clock pu l se s or they may originate from an external source or occur at prescribed intervals or at random. In a c o u n t e r the seq u ence o f st a t e s m a y f o l l o w b i na ry c o u n t or any other sequence. Counters are found in almost all equipment containing digital system

Binary Counter Binary Counter : A counter that follows the binary sequence is called a Binary counter. An n-bit Binary Counter consists of n flipflops and can count in binary from to 2 n -1 . For eg. Binary counter for two digits is as follows: Pr e s en t St a t e A B N e x t St a t e A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

Applications of Counters Some of the applications of counters in a sequential circuits are as follows: T o c o u n t the num b e r o f o cc u r an c e s Generating Timing sequences Count up or down Increment or decrement count Sequence events Divide frequency Address memory As temporary memory

Two principal categories Counters are divided in two categories, these are: Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse, and then each successive flip-flop is clocked by the Q or Q' output of the previous flip-flop. Synchronous Counters - all memory elements are simultaneously triggered by the same clock.

Difference between Asynchronous and Synchronous Counter Sr. No . Key Synchronous Counter Asynchronous Counter 1 Trigger In case of Synchronous Counter, as the name suggests all the constituent flip flops are triggered with same clock simultaneously. In case of Asynchronous Counter there is triggering of different flip flops with different clock. 2 Speed As mentioned above in case of Synchronous Counter all flip flops are triggered altogether hence operation speed of counter become faster as compared to that of Asynchronous counter. Asynchronous Counter operation speed is comparatively slower than Synchronous counter. 3 Complexity As all flip flops are being coordinating with the clock hence the design and implementation is complex as compared to that of Asynchronous Counter. On other hand as output of one flip flop performing as input of next flip flop the design and implementation is quite simple in case of Asynchronous counter. 4 Sequence Synchronous Counter could be operated in any desired count sequence as it could get manipulated by changing the clock sequence. Asynchronous counter could operate only in fixed count sequence i.e., UP and DOWN. 5 Delay There is no propagation delay observed in case of Synchronous Counter. There is a subsequent propagation delay from one flip flop to another in case of Asynchronous Counter

Few other categories of counters: Apart from synchronous and asynchronous counters which are the major ones the other types of counters are as follows: – Ring counter – Johnson counter – Decade counter – Up–down counter

Asynchronous Counters Here flipflop output transition serves as a source for triggering other flip flops. Thi s means t h a t the clockpulse is p r o v i de d t o a s in g l e flip flop. Th e ch a n g e o f st a t e o f a g i v e n fli p f l o p i s depende n t on the states of other flipflops. In other words the flip flops are not triggered by s i m ul t a n o u s clock pul s e s bu t the t r a n s i t i o n s in o t he r flip flops. Propagation delays in an asynchronous (ripple-clocked) binary counter.

Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse. Also known as ripple counters , as the input clock pulse “ripples” through the counter – cumulative delay is a drawback. n flip-flops  a MOD (modulus) 2 n counter. (Note: A MOD- x counter cycles through x states.) Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider . Asynchronous (Ripple) Counters

Two-bit asynchronous counter Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all the flip-flops before counting starts. The 2-bit ripple counter circuit above has four different states, each one corresponding to a count value. Similarly, a counter with n flip-flops can have 2 N states. T h e nu m b e r o f st a t e s in a c o u n t e r is kn o wn a s its mod(mod u lo) number.

Up/down Counter UP/DOWN Counter U p counter an d d o wn counter i s comb i ned togeth e r to o bt ain an UP/DOWN counter. A mode control (M) input is also provided to select either up or down mode. A combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation. Type of up/down counters- UP/DOWN ripple counters UP/DOWN synchronous counter

Larger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters. Connect last-stage output of one counter to the clock input of next counter so as to achieve higher-modulus operation. Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter. Cascading Asynchronous Counters J J Q 1 Q CLK Q Q C C Q ' Q' K K J J Q 3 Q 2 J Q 4 Q Q Q C C C Q ' Q ' Q' K K K Modulus-4 counter Modulus-8 counter

Synchronous (Parallel) Counters Synchronous (Parallel) Counters Example: Synchronous decade/BCD counter (cont’d). T = 1 T 1 = Q 3 ' . Q T 2 = Q 1 . Q T 3 = Q 2 . Q 1 . Q + Q 3 . Q 1 Q 1 Q CLK T C Q Q' Q Q' Q 2 Q 3 T C Q Q' Q Q' T C Q Q' Q Q' T C Q Q' Q Q'
Tags