Presentation.pptx computer architecture 65344

Computer architecture

1. Computer architecture Assignment;- Name ;- Vikash kumar branch ;- bca (1 st ) Roll no ;- 259089 (b)

2. Question no . 1 Q1.A) perform the following Conversion . A) (101101)₂→ Decimal To covert to binary to decimal ,multiply each bit its Corresponding power of 2 and sum the results.

3. (b) (459)₁₀ → Hexadecimal To convert decimal to hexadecimal, repeatedly divide the
number by 16 and note the remainders.
459 ÷ 16 = 28, Remainder = 11 (B in Hex)
28 ÷ 16 = 1, Remainder = 12 (C in Hex)
1 ÷ 16 = 0, Remainder = 1
Reading the remainders from bottom to top gives the Hexadecimal equivalent.
Answer: (459)₁₀ = (1CB)₁₆

4. Q1. B) Perform the following arithmetic
operations:
• Subtract (37)10 from (59)10 using BCD subtraction.
• BCD represents each decimal digit with a 4-bit binary code.
• Convert numbers to BCD:
• (59)₁₀ = 0101 1001 (5 is 0101, 9 is 1001)
• (37)₁₀ = 0011 0111 (3 is 0011, 7 is 0111)
• Since we are subtracting a larger digit (7) from a smaller digit (9 in the units place), we use the 9’s
complement method for BCD subtraction.
• Find the 9’s complement of the subtrahend (37):
• 9’s complement of 3 is 6.
• 9’s complement of 7 is 2.
• So, the 9’s complement of 37 is 62.
• Add the minuend (59) to the 9’s complement of the subtrahend (62).
• 59 + 62 = 121
• The leftmost digit (1) is the “carry”. In BCD subtraction, if there is a carry, it indicates a positive result.

5. Q2. A) Simplify the Boolean expression
using K-Map:
• F(A,B,C,D) = Σ(0,1,2,5,8,9,10,13)
• Quad 1: Cells 0,2,8,10. (A’B’C’D’ + A’B’C’D + AB’C’D’ + AB’C’D). This simplifies
to B’D’ because A and C vary.
• Quad 2: Cells 0,1,8,9. (A’B’C’D’ + A’B’C’D + AB’C’D’ + AB’C’D). This simplifies
to B’C’ because A and D vary.
• Pair: Cells 5,13. (A’BC’D + ABC’D). This simplifies to BC’D because A varies. Simplified Expression: F(A,B,C,D) = B’D’ + B’C’ + BC’D • Answer: F = B’D’ + B’C’ + BC’D

6. Q2. B) A dataword 101100 is to be transmitted using the generator polynomial G(x) = x³ + x + 1. F ind the transmitted codeword using CRC. Represent the generator polynomial in binary.
• G(x) = x³ + x + 1 = 1*x³ + 0*x² + 1*x¹ + 1*x⁰
• Binary: 1011
• Determine the number of redundant bits ®.
• The highest power of G(x) is 3, so r = 3.
• Append r (3) zeros to the dataword
• Dataword: 101100 → Augmented dataword: 101100000
• Perform binary division: Divide the augmented dataword (101100000) by the divisor
(1011).
•Form the codeword:
• The remainder of the division is 010.
• Transmitted Codeword = Original Dataword + Remainder = 101100010
•Answer: The transmitted codeword is 101100010.

7. Q3. A) Differentiate between Half Adder and Full Adder. Truth Table (Half Adder) Logic Diagram (Half Adder) Inputs A,BA, BA,B → XOR gate → Output = SUM Inputs A,BA, BA,B → AND gate → Output = CARRY

8. •Truth Table (Full Adder) •Logic Diagram (Full Adder) •Inputs A,BA, BA,B → Half Adder #1
→ gives Sum1 and Carry1 •Sum1 + Cin → Half Adder #2 →
gives Final SUM and Carry2 •Final Carry (Cout) = Carry1 + Carry2 (OR gate)

9. Q3. B) Explain SR, JK flip flop & their working with truth tables. 1. SR Flip-Flop (Set-Reset)
• Explanation: It is the simplest
flip-flop, with two inputs: S (Set) and
R (Reset). When S=1, the output Q
is set to 1. When R=1, Q is reset to
0. The condition S=R=1 is forbidden
as it leads to an invalid state (Q and
Q’ both being 1).
• Truth Table (Clock-Triggered SR Flip-Flop): 2. JK Flip-Flop Explanation: It is a refinement of the SR flip-flop. The inputs are labeled J (like Set) and K (like Reset). The main advantage is that the invalid state of the SR flip-flop is defined in the JK flip-flop. When J=K=1, the output toggles (changes to the opposite state).

10. Truth Table:

11. Q4. A) Design and explain the working of a 4-to-1 multiplexer. Q )Write the truth table and logic diagram.
Explanation: A 4-to-1 multiplexer (MUX) is a digital switch that has 4 data inputs (I₀, I₁, I₂, I₃), 2 select lines
(S₁, S₀), and 1 output (Y). The select lines determine which one of the 4 input lines is routed to the single
output.
Working: The binary number on the select lines (S1S0) acts as an address, choosing a specific input.
If S1S0 = 00, input I₀ is connected to Y.
If S1S0 = 01, input I₁ is connected to Y.
If S1S0 = 10, input I₂ is connected to Y.
If S1S0 = 11, input I₃ is connected to Y.

12. B) .Explain T & D flip flop & their working with truth tables. •T Flip-Flop (Toggle)
•Explanation: The T flip-flop has a single input T (Toggle). When
T=1, the output toggles on the next clock edge (i.e., it changes
to the complement of its current state). When T=0, the output
remains the same (holds its state). It is useful for designing counters. •Truth Table:

13. 2. D Flip-Flop (Data or Delay)
•Explanation: The D flip-flop has a single input D (Data). The
value present at the D input is transferred to the output Q on the
active clock edge. It is commonly used for data storage
(registers) and for delaying the passage of data by one clock
cycle.
•Truth Table: •Essentially, Q_n+1 = D.

14. T hank you