Programmable Logic Array

Slides that covers programmable logic array definition, example, advantages, disadvantages..

1. Programmable Logic Array (PLA) Module 4

2. What is PLA? Programmable Logic Array is a programmable logic device having programmable AND gates and OR gates. These devices are basically programmed to implement the Boolean functions. PLA allows the implementation of any random boolean function present in SOP form using programmable technique.

3. Components The fundamental components of PLAs are Input buffer Programmable AND gate matrix Programmable OR gate matrix.

4. Input Buffer Basically buffers at the input are used to reduce the loading of the sources. The buffer generates the inverted and non-inverted input as its output. Input buffers are basically a combination of NOT gates. Number of input buffers = Total number of variables present in a boolean expression

5. AND Matrix AND matrix is used to give product terms as output. Basically each AND gate in the circuit provides the product of the terms present in the inverted and non-inverted form at its input. Number of programmable AND gates = Number of minterms in the expression (without repetition) INPUT BUFFER OR MATRIX

6. OR Matrix An OR logic gate is designed to perform addition. Thus the OR matrix provides the addition of the input as the output. Number of programmable OR gate = Number of functions in the expression AND MATRIX

7. Implementation Consider the given boolean expression and reduce it to its minimum SOP form. Once the expression is reduced then firstly, form the connections of the input buffer. Further, we need to generate product terms, for which the desired input at the AND matrix must be provided. After forming the connections of AND matrix, proceed further and establish the connection for OR matrix.

8. Suppose the boolean expressions to be realized are as follows: Z1 = AB + A’C’ Z2 = A’B’C + A’B Now further the output of the input buffer must be provided to the AND matrix to have the desired product term. Example

9. The number of AND gates in the matrix will be equal to the number of minterms and that too without repetition. And here we are having 4 non-repetitive minterms. So total 4 AND gates must be present in the matrix. AB , A’C’ , A’B’C , A’B Example (Continuation) Now the output of the AND gate must be provided to OR matrix to have the desired combinations of SOP.

10. The number of programmable OR gates in the matrix must be equal to the number of functions. And here we are having two functions thus we will have two OR gates. Thus, for these expressions the logic circuit, comprising of programmable AND gate and programmable OR gate is given as: Example (Continuation)

11. Figure

12. Advantages Design checking is easy and design change is also easy. Layout is simpler than random logic gate networks, and thus is far less time consuming. Only the connection mask needs to be custom made. When new IC fabrication is introduced we can use previous design information with ease but without change, making adoption if the new technology quick and easy .

13. Disadvantages Random-logic gate networks have higher speed than PLA’s. Random-logic gate networks occupy smaller chips areas than PLA’s although the logic design and the layout of random -logic gates networks are far more tedious and time-consuming. Also, with large production volumes, random-logic gate networks are cheaper then PLAs.

14. Application A microprocessor chip uses many PLA’s as they are easy to design, change an check. PLA’s are used in control logic, which is complex and requires many changes, even during its design. Also, PLA’s are used for code conversions, microprogram address conversion, decision tables, bus priority resolvers and memory overlays.

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