Register and counter

MCQ for Register and Counters

1. Analog and Digital Electronics Quiz (Registers and Counters) By: Dr. Mayank Pandey Assistant Professor Department of Physics and Electronics. Kristu Jayanti College (Autonomous), Bangalore

2. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________ a) 1110 b) 0001 c) 1100 d) 1000

3. 2 . The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains a) 10111000 b) 10110111 c) 11110000 d) 11111100

4. 3. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse? a) 1101000000 b) 0011010000 c) 1100000000 d) 0000000000

5. 4. On the second falling edge of clock in ring counter, if the generated output of second clock pulse is ' 0100', what will be the output after the  fourth clock pulse ? a. 1000 b. 0001 c. 0010 d. 0000

6.   5. What decimal value is required to produce an output at "X" ? a) 1 b) 1 or 4 c) 2 d) 5

7. 6. Which of the following is an invalid output state for an BCD counter? a) 1110 b) 0000 c) 0010 d) 0001

8. 7. A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct ? (NO)

9. 8. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse? a) 1101 b) 1011 c) 1111 d) 0000

10. 9. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________. 15 ns 30 ns 45 ns 60 ns

11. 10. T he circuit shown below is a ________. Draw the output waveform parallel in/serial out register serial in/parallel load register Multiplexer De-multiplexer

12. (a) ( b) ( c) Problem 1:   Write a boolean expression for the output, Q, in terms of the inputs A, B, and C.                                                                               

13. Problem 2.  Draw a circuit to realize each of the expressions using AND gates, OR gates and Invertors.

14. Input   Output D C B A W X Y Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X 1 1 1 1 X X 1 1 1 1 X X 1 1 1 1 X X Problem 3.   In the truth table below, the inputs are A, B, C, and D.  Use a Karnaugh map to come up with a minimum sum of products form when: the output is W the output is X the output is Y the output is Z

15. Problem 11.   The flip-flops in the drawing below are positive edge triggered D flip flops.  Let Q2, Q1, Q0 = 1,0,0 initially.  Plot the clock, Q2, Q1 and Q0 until the outputs begin to repeat.