s-box based random number generation for computing

Random Number generation

1. S-BOX BASED RANDOM NUMBER GENERATION FOR STOCHASTIC COMPUTING Submitted By Y.MALLIKA - 17E45A0408 M.RAJU - 16E41A0495 U.SATHISH - 16E41A04E2 UNDER THE ESTEEMED GUIDANCE OF V. Naveen , Asst. Professor, Dept. of ECE, SDES . SREE DATTHA INSTITUTE OF ENGINEERING AND SCIENCE DEPARTMENT OF ECE (2017 -2020) 1

2. Introduction: Stochastic circuits offer tremendous area and power-consumption benefits at the expense of computational inaccuracies. They require random number sources to implement stochastic number generators for all of their inputs. It is common for SCs as it takes largely primary and auxiliary inputs, as it occupies 80% of circuit area. So sharing of Random number generators is important in stochastic computing. 2

3. This sharing leads to large correlation errors that errors have to resolved by costly decorrelation methods. As we use Linear Feed back Shift register as RNS. Their deterministic and linear behaviour can interfaces with common used decorrelation methods which leads to systematic computational errors and limiting the possibilities of sharing LFSRs with SNRs. So we have a proposal Pseudo random number generator SBoNG for stochastic circuits that combines and LFSR with non linear s-box function. 3

4. Existing system: Digital Clock Manager based tunable BFD–TRNG 4

5. True Random Number Generators (TRNGs) have become indispensable component in many cryptographic systems, including PIN/password generation, authentication protocols, key generation, random padding and noice generation. We have a simple post-processing unit using a Von Neumann Corrector (VNC). TRNGs are often biased, this means for example that on average their output might contain more ones than zeros and therefore does not correspond to a uniformly distributed random variable. This effect can be balanced by different means, but this post-processing reduces the number of useful bits as well as the efficiency of the generator. 5

6. Proposed system: 6

7. It is based on an LFSR in combination with the 4 bit S-box of a small-scale version of AES. The SBoNG has an internal state S whose length has to be a multiple of 4. The LFSR length should equal that of S. SBoNG is its ability to generate multiple, nearly independent SNs from one random number. One SBoNG instance can be shared between multiple SNGs, where each SNGrotates the state by a different number of bits. 7

8. Software: Xilinx ISE : Xilinx ISE(Integrated synthesis environment) is a software tool produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize their design, perform timing analysis, examine RTL diagrams, simulate a designs reaction to different stimuli, and configure that target device with the programmer. Modelsim : Modelsim is a multi-language HDL simulation environment for simulation of HDL such as VHDL, Verilog modelsim can be used independently, or in conjunction with Xilinx ISE. 8

9. Advantages: They can provide high acceptable to high processing rate at much lower cost and faster design cycle time. It provides the greater design flexibility. The circuit design is simple and well suited for FPGA design flow. 9

10. Applications: It is used in cryptography. It is used in medical (ECG). We can use it in simulation. It is also used in text to speech converter. It is used in numerical analysis. 10

11. Conclusion: We have proposed the SBoNG , a novel pseudo-random number generator that replaces the traditional LFSR as the RNS in the SNGs of stochastic circuits. SNs generated by an SBoNG show better autocorrelation and cross-correlation properties than SNs generated by the standard method, due to the non-linear component in our construction. 11

12. Future Scope: Methods for sharing LFSRs between SNGs should be improved by using FIR filter so that we can combine the ability of an LFSR to generate exact SNs of maximum sequence length with the ability to derive multiple uncorrelated SN’s from one SBoNG instance. 12

13. References: [1] D. B. Thomas and W. Luk , “The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures,” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, March 2012. [2] D. B. Thomas and W. Luk , “FPGA-optimized uniform random number generators using lot and shift registers,” in Proc. Int. Conf. Field Program. Logic Appl., 2010, pp. 77–82. [3] D. B. Thomas and W. Luk , “FPGA- optimized high - quality uniform random number generators,” in Proc. Field Program. Logic Appl. Int.Conf ., 2008, pp. 235-244. [4] D. B. Thomas and W. Luk , “High quality uniform random number generation using LUT optimized state-transition matrices,” J. VLSI Signal Process., vol. 47, no. 1, pp. 77–92, 2007. [5] F. Panneton , P. L’Ecuyer , and M. Matsumoto, “Improved long period generators based on linear recurrences modulo 2,” ACM Trans. Math. Software, vol. 32, no. 1, pp. 1–16, 2006. 13

14. THANK YOU 14