SDC_file_vlsi_designFlow synopsys design.pptx

SDC file VLSI

1. SDC file Synopsys design constraint Index: SDC definition SDC file usage in VLSI design flow Significance of SDC Various components of SDC

2. 1. SDC file SDC or the Synopsys design constraint file sets the time, power and other constraints for the entire design . It communicates various environmental conditions and block-to-block information from and to the DUA: Design under analysis.

3. 2. SDC file usage in VLSI design flow SDC file in first created by the designers as an input to the Logic synthesis stage. Later, as we see in the diagram, the SDC file is changed and refined more by the tool/designer as per any optimizations/modifications done during the flow. .lib, . sdc , .v Netlist, sdc STA

4. 3. Significance of SDC file In the case of multi-block designs, it is important to communicate the boundary conditions between teams working on different blocks of a larger design. This helps to provide a better convergence at the time of combining the various sections to create a complete chip for final tapout . C B D A These constraints guide the design towards meeting design’s performance, power, and size targets. SDC guides the tool at each design flow and is used not only in synthesis but is propagated to PnR and STA check also.

5. 4. Various components There are various constraints seen inside SDC, some of them are as follows, Clock period, waveform, uncertainty, latency etc Input/output delays Input driving cell Output load Max transition, max capacitance, max fanout Environment conditions Wireload Etc. Image source :Li-Yang Huang presentations

6. 4.1 Design rule limits DRV constraints in the SDC are design-specific constraints that apply to all nets or specific groups of nets across the design, not just individual cells. Note: Similar max_cap , max_trans values are mentioned in the technology library of the cells. But those are cell-specific. Adjacent Design DUA Violations Reasons Max_transition - If transition is very slow, in case of a cmos inverter, we see a peak of current at intermediate stage, leading to high power consumption. - Thus a sharp trans. ould help save power dissipation. Max_fanout To control the amount of connections to the input pins of cells connected a drive. Max_cap - To control the overall loads that each cell drives is under a limit for reliable transmission of the signal. - This also helps keep the charges at a limit, which in turn keeps the current density of a net in the limit, which in turn helps to reduce the effects of EM.

7. 4.1 (ii.) set_max_fanout (specifies a fanout limit on all pins in design), set_max_area (for a design); however these checks apply for synthesis and not for STA Violations set_max_capacitance value #object_list specifies the max capacitance for ports or on a design. # If for a design, it specifies the max capacitance for all # pins in the design

8. 4.2 Input/Output delays set_input_delay –clock clk –max 6.4 [ get_ports in1] set_input_delay –clock clk –min 4.4 [ get_ports in1] set_output_delay –clock clk –max 5.3 [ get_ports out1] set_output_delay –clock clk –min 4.4 [ get_ports out1]

9. 4.2 (ii.)

10. 4.3 Input drive cell and output load set_driving_cell –library name – lib_cell name –pin {C} [ all_inputs ] set_load [ load_of “ inst_name ” ] [ all_outputs ] Driving cell affects the data arrival time at the input ports. By specifying driving cell, tool accurately calculates the rise/fall transition time at input ports. The output load determines the delay with which the signal transmits from output port. Delay = func (input transition, output load)

11. 4.3 (ii.)

12. 4.4 Clock properties Period Waveform Uncertainty Latency Exceptions Multicycle False path Half cycle path Case analysis Disable timing arcs Virtual clocks create_clock -name CLKM -period 10 -waveform {0 5} \ [ get_ports CLKM] set_clock_uncertainty -setup 0.3 [ all_clocks ] set_clock_transition -rise 0.2 [ all_clocks ] set_clock_transition -fall 0.15 [ all_clocks ]

13. Without the -source option, the set_clock_latency command defines the clock network latency - this is the latency from the clock definition point in the DUA to the clock pin of a flip-flop Note that the source latency does not affect paths that are internal to the design and have the same launch clock and capture clock. The set_clock_uncertainty specifies a window within which a clock edge can occur. The uncertainty in the timing of the clock edge is to account for several factors such as clock period jitter and additional margins used for timing verification. Every real clock source has a finite amount of jitter - a window within which a clock edge can occur. The clock period jitter is determined by the type of clock generator utilized 4.4 (ii.)

14. Virtual clock A virtual clock is a clock that exists but is not associated with any pin or port of the design. It is used as a reference in STA analysis to specify input and output delays relative to a clock. Eg : clock driving input port ROW_IN is CLK_SAD. Ques. How does one specify the IO constraint on input port ROW_IN in such cases? The same issue occurs on the output port STATE_O. 4.4 (iii.)

15. create_clock -name VIRTUAL_CLK_CFG -period 8 \ -waveform {0 4} create_clock -period 10 [ get_ports CLK_CORE ] set_input_delay -clock VIRTUAL_CLK_SAD -max 2.7 \ [ get_ports ROW_IN] set_output_delay -clock VIRTUAL_CLK_CFG -max 4.5 \ [ get_ports STATE_O] 4.4 (iv.)

16. Other timing exceptions set_case_analysis : Specifies constant value on a pin of a cell, or on an input port. set_case_analysis 1 UCORE/UMUX1/CLK_SEL[1] #no timing path checked for PLLCLK set_disable_timing : Breaks a timing arc of a cell. 4.4 (v.)

17. set_false_path : Specifies paths that are not real which implies that these paths are not checked in STA. set_false_path –through/-from [ get_pins UMUX0/S] # Any path going through this pin is false. Ignored for timing analysis Note: if no datapaths from clk1 to clk2 domain, then independent, thus there will be no timing path that starts from one clock domain and ends in the other clock domain. 4.4 (vi.)

18. IMAGES COURTESY: J Bhaskar book STA set_multicycle_path : Specifies paths that can take longer than one clock cycle create_clock -name CLKM -period 10 [ get_ports CLKM] set_multicycle_path 3 -setup \ -from [ get_pins UFF0/Q] \ -to [ get_pins UFF1/D] 4.4 (vii .)