Semiconductor memory

This Presentation has the details about the Semiconductor memory

1. Semiconductor Memories
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2. Semiconductor memory is an electronic data storage
device, often used as computer memory, implemented 
on a semiconductor-based integrated circuit.
Introduction
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3. Semiconductor memory
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4. Example of Semiconductor memory
Examples  of  semiconductor  memory  includes Non-volatile
memory  such  as  Read-only memory (ROM), 
Magnetoresistive Random Access Memory  (MRAM),  and 
Flash memory.
It  also  includes volatile memory such  as Static Random
Access Memory (SRAM)
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5. Cont.,
These  memories  can  be  constructed  to  store  large 
amount of data entirely within a computer system.
The number of locations and the size of storing data
may vary from memory to memory.
Each location is called Memory cell.
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6. Memory cell operation
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7. Memory cell
The memory cell is used to store single bit of information.
The memory cell is fabricated by using either bipolar Metal
Oxide Semiconductors (MOS) or Complementary Metal
Oxide Semiconductors (CMOS).
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8. Semiconductor memory classification
RWM NVRWM ROM
EPROM
E
2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
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9. Memory Architecture: Decoders
Word 0
Word 1
Word 2
Word N-1
Word N-2
Input-Output
S
0
S
1
S
2
S
N-2
S
N_1
(M bits)
Storage
Cell
M bits
N
W
o
r
d
s
Word 0
Word 1
Word 2
Word N-1
Word N-2
Input-Output
(M bits)
Storage
Cell
M bits
D
e
c
o
d
e
r
A
0
A
1
A
K-1
S
0
N words => N select signals
Too many select signals
Decoder reduces # of select signals
K = log2N
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10. Array-Structured memory Architecture
Input-Output
(M bits)
R
o
w
D
e
c
o
d
e
r
A
K
A
K+1
A
L-1
2
L-K
Column Decoder
Bit Line
Word Line
A
0
A
K-1
Storage Cell
Sense Amplifiers / Drivers
M.2
K
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
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11. Hierarchical memory Architecture
Global Data Bus
Row
Address
Column
Address
Block
Address
Block Selector Global
Amplifier/Driver
I/O
Control
Circuitry
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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12. Memory Timing Definitions
READ
WRITE
DATA
Read Access Read Access
Read Cycle
Data Valid
Data Written
Write Access
Write Cycle
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13. Memory Timing Approaches
Address
Bus
RAS
CAS
RAS-CAS timing
Address
Bus
Address
Address transition
initiates memory operation
DRAM Timing SRAM Timing
Row AddressColumn Address
MSB LSB
Multiplexed Adressing Self-timed
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14. Read-Write Memories (RAM)
Static (SRAM)
Data stored as long as supply is applied
Large (6 transistor/cell)
Fast
Differential
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15. Read-Write Memories
Dynamic (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
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16. 6- Transistor CMOS SRAM Cell
VDD
Q
Q
M1 M3
M4M2
M5
BL
WL
BL
M6
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17. CMOS SRAM Analysis (Write)
V
DD
Q = 1
Q = 0
M1
M4
M5
BL = 1
WL
BL = 0
M6
V
DD
k
n M6,
V
DD
V
Tn
–( )
V
DD
2
-----------
V
DD
2
8
-----------–
è ø
æ ö k
p M4,
V
DD
V
Tp
–( )
V
DD
2
-----------
V
DD
2
8
-----------–
è ø
æ ö=
k
n M5,
2
--------------
V
DD
2
----------- V
Tn
V
DD
2
-----------
è ø
æ ö–
è ø
æ ö
2
k
n M1,
V
DDV
Tn–( )
V
DD
2
-----------
V
DD
2
8
-----------–
è ø
æ ö=
(W/L)n,M5 ³ 10 (W/L)n,M1
(W/L)
n,M6 ³ 0.33 (W/L)
p,M4
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18. CMOS SRAM Analysis (Read)
VDD
Q = 1
Q = 0
M1
M4
M5
BL
WL
BL
M6
V
DD
V
DD
VDD
C
bitC
bit
k
n M5,
2
---------------
V
DD
2
------------ V
Tn
V
DD
2
------------
è ø
æ ö
–
è ø
æ ö
2
k
n M1,
V
DD
V
Tn
–( )
V
DD
2
------------
V
DD
2
8
------------–
è ø
æ ö
=
(W/L)n,M5 £ 10 (W/L)n,M1 (supercedes read constraint)
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19. 6T- SRAM - Layout
V
DD
GND
QQ
WL
BLBL
M1 M3
M4M2
M5 M6
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20. 3- Transistor DRAM Cell
M2
M1
BL1
WWL
BL2
M3
RWL
C
S
X
WWL
RWL
X
BL1
BL2
VDD-VT
DV
V
DD
VDD-VT
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = V
WWL-V
Tn
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21. 3-T DRAM Layout
BL2 BL1 GND
RWL
WWL
M3
M2
M1
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22. DRAM Cell
1T DRAM requires a sense amplifier for each bit line, 
due to charge redistribution read-out.
DRAM  Memory cells are single ended  in contrast to 
SRAM cells.
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23. 1-T DRAM cell
(a) Cross-section
(b) Layout
Diffused
bit line
Polysilicon
plate
M1 word
line
Capacitor
Polysilicon
gate
Metal word line
SiO
2
n
+
Field Oxide
Inversion layer
induced by
plate bias
n
+
poly
poly
Used Polysilicon-Diffusion Capacitance
Expensive in Area
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24. Semiconductor Memory Trends
Memory Size as a function of time: x 4 every three years
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25. Semiconductor Memory Trends
Increasing die size
factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation
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26. Semiconductor Memory Trends
Technology feature size for different SRAM generations
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27. The End
……. Thank You …….
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