Seminar Report on A Novel Design of High Speed Multiplier Using Hybrid Adder Technique

Mid Semester - Seminar Report on A Novel Design of High Speed Multiplier Using Hybrid Adder Technique

1. A Novel Design of High Speed Multiplier Using
Hybrid Adder Technique
A seminar report submitted for Mid Semester Evaluation
NATIONAL INSTITUTE OF TECHNOLOGY
SILCHAR

2. Introduction
Multipliers are essential components in VLSI (Very Large Scale Integration) systems,
commonly used in high-performance computing and digital signal processing
applications. However, achieving a balance between speed, power consumption, and
area efficiency remains a challenge in traditional multiplier designs. This report
presents a novel approach that combines two advanced adders, the Kogge Stone Adder
(KSA) and the Brent Kung Adder (BKA), to design a high-speed multiplier. The goal
of this approach is to reduce computation delay and increase speed of operation.
Methodology
To design the hybrid multiplier, two key adder types are used:
Kogge Stone Adder (KSA):
Known for its high speed, this adder is designed to perform fast additions, making it
ideal for applications where speed is crucial. However, it requires more hardware
resources and consumes more power compared to simpler designs.
Brent Kung Adder (BKA):
The Brent Kung adder is more area-efficient and consumes less power than the Kogge
Stone adder. Although it operates at a slower speed, it uses fewer gates and
interconnections, making it a more compact and power-friendly option.
By combining these two adders, the hybrid multiplier leverages the speed advantage of
the Kogge Stone adder while benefiting from the lower area and power consumption of
the Brent Kung adder.
The hybrid multiplier was implemented using an 8-bit multiplier, with partial product
calculated and added using the hybrid adder. The design was simulated using Xilinx
ISE Design Suite and tested on an Artix-7 FPGA. The performance of the hybrid
multiplier was evaluated against other designs using parameters such as delay and
speed of operations.

3. Results and Discussion
The hybrid multiplier was compared with traditional multiplier designs that use
either the Kogge Stone Adder, Brent Kung Adder. The results showed significant
improvements in speed and delay:
The Brent Kung adder had a delay of 4.315 ns due to its simpler structure and
lower area usage.
The Kogge Stone adder had a delay of 4.618 ns, despite being faster in theory,
the complexity and routing overhead in FPGA implementation contributed to a
higher delay.
The hybrid multiplier achieved a delay of 4.062 ns, which is 6.22% faster than the
Brent Kung adder-based multiplier and 13.68% faster than the Kogge Stone
adder-based multiplier.
The trade-off
for using the hybrid approach is a slightly higher logic complexity compared to the
individual Brent Kung or Kogge Stone adders. However, this complexity is outweighed
by the significant performance benefits, especially in terms of speed.
Conclusion
This report presents a high-speed multiplier design based on a hybrid adder that
combines the features of the Kogge Stone Adder and the Brent Kung Adder. The
hybrid design optimizes delay and speed making it highly suitable for applications
requiring high-performance arithmetic operations. Future work can focus on reducing
the logic complexity of the hybrid design while maintaining its speed and delay
advantages.

4. References
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Design of High Speed Multiplier Using Hybrid Adder Technique," 2024 3rd
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