Sequential circuits digital logic sesign

Sequential circuits

1. 1
Computer Logic & Design
Fall 2005t
0
t
4
t
5
t
6
t
1
t
2
t
3
A
B
F
Sana Ullah Qaisar
Lecturer, Telecom. Engineering
NUCES, Islamabad

2. 2
Counters
−Function Table
Input Output
Clock Pulses F
2
F
1
F
0
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1

3. 3
Counters
−3 bit Asynchronous CounterJ
Q
Q
K
SET
CLR
J-K flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
J-K flip-flop 2
1
J
Q
Q
K
SET
CLR
J-K flip-flop 3
1
F0 F1 F2 CLOCK
Input
F0
Output
F1
Output
t1 t2 t3 t4 t5 t6 t7 t8
F2
Output

4. 4
Counters
−Down Counters
3-bit Asynchronous Down-CounterJ
Q
Q
K
SET
CLR
J-K flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
J-K flip-flop 2
1
J
Q
Q
K
SET
CLR
J-K flip-flop 3
1
F0 F1 F2

5. 5
Counters
−Timing diagram of a 3-bit Asynchronous Down-
CounterCLOCK
Input
t1 t2 t3 t4 t5 t6 t7 t81F 0F 1F 0F 2F t9

6. 6
Counters
−Down Counter with truncated sequence
from 111 to 011
Sets at 010 J
Q
Q
K
SET
CLR
J-K flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
J-K flip-flop 2
1
J
Q
Q
K
SET
CLR
J-K flip-flop 3
1
F0 F1 F2

7. 7
Counters
−Down Counter with truncated sequence
from 111 to 011
Sets at 010J
Q
Q
K
SET
CLR
flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
flip-flop 2
1
J
Q
Q
K
SET
CLR
flip-flop 3
1
F0 F1 F2

8. 8
Counters
−diagram of a counter configured to count a
truncated sequenceCLOCK
Input
t1 t2 t3 t4 t5 t6 t7 t8
1F
0
F
1F
0
F
2F
t9
2F

9. 9
Counters
−Synchronous Counters
2-bit Synchronous CounterJ
Q
Q
K
SET
CLR
J-K flip-flop 1
1
CLK
F1
J
Q
Q
K
SET
CLR
J-K flip-flop 2
F0

10. 10
Counters
−Timing diagram of a 2-bit Synchronous CounterCLOCK
Input
F0
Output
F1
Output
t1 t2 t3 t4 t5 t6 t7 t8

11. 11
Counters
−Implementation of Synchronous Counters larger
than 2-bits requires the use of an AND gate
A 3-bit Synchronous CounterJ
Q
Q
K
SET
CLR
flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
flip-flop 2
J
Q
Q
K
SET
CLR
flip-flop 3
F0 F1 F2

12. 12
Counters
−Timing diagram of a 3-bit Synchronous CounterCLOCK
Input
F0
Output
F1
Output
t1 t2 t3 t4 t5 t6 t7 t8
F2
Output
AND
gate
Output

13. 13
Counters
−3-bit Synchronous Counter
At interval t4, the 3-bit counter should count from
state 011 to 100
At interval t8 the counter should count from state
111 to 000
At both the intervals the F2 output of the third flip-
flop toggles to logic 1 and logic 0 respectively
when the outputs F0 and F1 are both at logic 1

14. 14
Counters
F3F2F1F0 F3F2F1F0
0000 1 0 00
0001 1 0 01
0010 1 0 10
0011 1 0 11
0100 1 1 00
0101 1 1 01
0110 1 1 10
0111 1 1 11

15. 15
Counters
−4-bit Synchronous Counter
−The fourth flip-flop changes its state when the
outputs of the first three flip-flops are at logic 1
−when the 4-bit counter is counting from 0111 to
1000 and 1111 to 0000J
Q
Q
K
SET
CLR
flip-flop 1
CLK
J
Q
Q
K
SET
CLR
flip-flop 2
J
Q
Q
K
SET
CLR
flip-flop 3
J
Q
Q
K
SET
CLR
flip-flop 4
1
F0
F1 F2 F3

16. 16
Counters
−4-bit Synchronous Decade Counter
Input Output
Clock Pulses F
3
F
2
F
1
F
0
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1

17. 17
Counters
−4-bit Synchronous Decade CounterJ
Q
Q
K
SET
CLR
flip-flop 1
CLK
J
Q
Q
K
SET
CLR
flip-flop 2
J
Q
Q
K
SET
CLR
flip-flop 3
J
Q
Q
K
SET
CLR
flip-flop 4
1
F0 F1
F2 F3

18. 18
Counters
−Timing diagram of a Synchronous Decade
CounterCLOCK
Input
F0
Output
F1
Output
t1 t2 t3 t4 t5 t6 t7 t8
F2
Output
F3
Output
t9 t10

19. 19
Counters
−3-bit Synchronous Down CounterJ
Q
Q
K
SET
CLR
flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
flip-flop 2
J
Q
Q
K
SET
CLR
flip-flop 3
F0 F1 F2

20. 20
Counters
−Function Table
Input Output
Clock Pulses F
2
F
1
F
0
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1

21. 21
Counters
−Up-Down Synchronous CounterJ
Q
Q
K
SET
CLR
flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
flip-flop 2
J
Q
Q
K
SET
CLR
flip-flop 3
F0 F1 F2DOWN/UP

22. 22
Counters
−Up-Down Synchronous CounterJ
Q
Q
K
SET
CLR
flip-flop 1
1
CLK
J
Q
Q
K
SET
CLR
flip-flop 2
J
Q
Q
K
SET
CLR
flip-flop 3
F0 F1 F2DOWN/UP

23. 23
Counters
−Timing diagram of an Up-Down Synchronous
CounterCLOCK
Input
F0
Output
F1
Output
t1 t2 t3 t4 t5 t6 t7 t8
F2
Output
t9 t10
UP DOWN UPDOWN/UP

24. 24
Counter ApplicationsDiv by 10Div by 6Div by 10Div by 6Div by 10FF
Div by 5Div by 10
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
Wave-
Shaping
Circuit
50Hz
220v AC
signal
50 Hz
5v signal
1 Hz
5v signal
Seconds Counter
Divide by 60
Minutes Counter
Divide by 60Hours Counter
Divide by 50
Counter

25. 25
Counter ApplicationsDiv by 10Div by 6Div by 10Div by 6Div by 10FF
Div by 5Div by 10
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
BCD-7
Segment
Decoder
a
b
c
d
e
f g
Wave-
Shaping
Circuit
50Hz
220v AC
signal
50 Hz
5v signal
1 Hz
5v signal
Seconds Counter
Divide by 60
Minutes Counter
Divide by 60Hours Counter
Divide by 50
Counter