SID 2009 Presentation

1. Honeywell Confidential1
Transparent Organic PlanarizingFilms for Low
Temperature Display Applications
Edward W. Rutter, Jr.,
Ahila Krishnamoorthy, Joseph T. Kennedy
Honeywell Electronic Materials, 1349 Moffett Park Drive, Sunnyvale CA 94089
Jeremy Burroughes, Sharmil Ghouse, Jonathan Halls and Chris Newsome
Cambridge Display Technology Ltd, Unit 12, Cardinal Business Park, Godmanchester,
6Cambridgeshire, PE29 2XG, UK
June 4, 2009

2. SID49.6 June 4, 2009
ƒMaterial Characteristics:
•Completely organic film
•Low temperature cure:
- Single hotplate bake: 120-200°C, 60-120 s
•Film thickness covers a wide range (up to 3 µm single coat, >12
µm multiple coats)
•Excellent gap-fill and planarization
•High optical transmittance
•Readily etched using oxygen-based plasma (for pattern transfer)
•Thermally stable, low outgassing
ƒIntegration Requirements:
•Process temperature (for OTFT must be below 150°C)
•Must withstand subsequent processes (SED, dry/wet etch, strip,
clean)
Many existing materials cure >
200°C, so cannot be used
for OTFT or plastic substrates
ACCUFLO
®
T-31

3. SID49.6 June 4, 2009
0%
20%
40%
60%
80%
100%
80 130 180 230
Bake Temperature (°C/60 s)
% Film Retention
ABDC
Low Temperature Curing
• Several variations made from “C” that differ in cure temperature
• Curing measured by film retention after exposure to PGMEA (60 s puddle) –aggressive test
• Multiple bakes may be performed to enhance reflow (planarization) prior to cure
• Crosslinking temperature lowered ~ 110°C to 130°C

4. SID49.6 June 4, 2009
0
20
40
60
80
100
250 450 650 850 1050
Wavelength (nm)
%T
Glass Blank ANext Gen
Optical Transmittance
• Very high optical transmission from 400 nm to 1100 nm (Formulation A shown)
• At 550 nm, optical transmittance is 97% relative to glass substrate
• Next Gen formulation permits high transmittance to be extended into the UV
n = 1.62, k= 0.0001 at 633 nm 150°C bake

5. SID49.6 June 4, 2009
Field
area
Dense trenches
0.22 µm to 6 µm
Substrate
• Coat (4000Å) • Two stage bake
Semiglobal Planarization
Trench to field height differential
Film thickness difference between field and array areas measured by high resolution
profilometry (over the entire array of different features)
Low, medium and high temperature versions of T31:
A and B are improvements relative to D
300
1600
850
400
0
400
800
1200
1600
2000
CDAB
Formulation
Step height difference (Å)
original (CDT)improved
Planarization
9000Å

6. SID49.6 June 4, 2009
Before
•Effective via fill – polymer re flows faster than crosslinking
Excellent via fill properties
Film thickness ~270 nm Via CD: 0.28 μm
Via depth: 0.6 μm
Coat & Bake Process:
Single coat
SS: 1500 rpm
Bake: 200°C/60 s
Excellent via fill properties
Film thickness ~270 nm Via CD: 0.28 μm
Via depth: 0.6 μm
Coat & Bake Process:
Single coat
SS: 1500 rpm
Bake: 200°C/60 s
After
coating
Via Fill (Formulation D)

7. SID49.6 June 4, 2009
Transparent Cathode
OLED Layers
Planarization
Polymer Dielectric
Gate: Metal eg. Al
Channel length 
5 – 200 μm
Source & Drain:
Metal eg. Au
Glass substrate
Semiconductor
500 nm
OLED contact
Via
Cross-sectional Device Architecture
• OTFTs potentially provide a route to low cost, lightweight flexible backplanes for OLED displays
• A planarization layer is required to protect the OTFTs and planarize the surface on which to
build the OLEDs
• Top emitting OLED using glass instead of flexible substrate in order to demonstrate proof of
concept using ACCUFLO
®
T-31 as TFT planarizing layer
• Film hotplate baked at 120°C for 120 s using 60°C/60 s pre- and post cure bakes (2.25 µm film
spin coated at 1000 rpm)
ACCUFLO
®
T-31

8. SID49.6 June 4, 2009
OTFT Device Characteristics with ACCUFLO
®
T-31
• I-V characteristics were measured before and after planarization under two different voltage
conditions
• The planarization process does not negatively impact the performance of the device
• Process optimization is required to improve the consistency of I
off
• Additional work required to understand how well ACCUFLO
®
T-31 protects the underlying
OTFT circuitry
• ACCUFLO
®
T-31 is a strong candidate for OTFT circuit planarization
TFT 1
Blue Before
Red After
V
ds
= -3V
V
ds
= -40V

9. SID49.6 June 4, 2009
0.9
0.95
1
1.05
1.1
0 50 100 150 200
Storage Time (Days)
Normalized Mw
A at 40°C B at 21°C
• Formulation D must be stored
refrigerated or the molecular weight
grows. Aging is more pronounced at
higher temperatures
• Formulations A shows no change in
molecular weight when stored at high
temperature (40°C) over 190 days
(accelerated aging)
• The average normalized Mw is
constant with low variation (~ 2%
relative) within the error of the GPC
method used to measure
• Improved formulations (A and B) are
more convenient for use since they
can be stored without refrigeration and
do not require equilibration times
associated with warming up for use
0
20
40
60
80
100
0 100 200 300 400
Storage Time (Days @ 40°C)
Normalized Mw
ADB at 21°C
0.022
0.987
B
0.020
0.968
A
StDev
Average
Formulation
Comparative Formulation Stability

10. SID49.6 June 4, 2009
Thank You for your Attention
ƒACCUFLO
®
T-31 demonstrates low temperature curing,
excellent gap-fill/planarizationand high optical transmittance
with outstanding formulation shelf-life
ƒThis combination of properties is enabling for use in
temperature-sensitive materials such as Organic TFTsand
plastic substrates
ƒThis material has demonstrated integration as a permanent
dielectric layer into an OTFT with no degradation of device
performance
Summary

11. SID49.6 June 4, 2009
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provided herein does not relieve the user from the responsibilit y of carrying out its own tests and
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recommendations to infringe any patent. The user should not assume that all toxicity data and
safety measures are indicated herein or that other measures may not be required.