Stick Diagram

1. Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

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4. Stick Diagram A stick diagram is a graphical view of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

5. Stick Diagram Represents relative positions of transistors Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers In Out V DD GND Inverter A Out V DD GND B NAND2

6. Stick Diagram Metal (BLUE) Polysilicion (RED ) N-Diffusion (Green) P -Diffusion (Brown) Contact / Via Layers

7. Jhon P. U Stick Diagrams Cartoon of a layout. Shows all components. Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc.

8. Jhon P. U 5 V Dep V out Enh 0V V in 5 v 0 V V in 5 v

9. Jhon P. U Parallel Connected MOS Patterning x y A B X X X A B x y

10. Jhon P. U Alternate Layout Strategy A B x y X X X X x A B y

11. Jhon P. U Designing MOS Arrays A B C y x y x A B C

12. Jhon P. U The CMOS NOT Gate X X X X Vp Gnd Gnd n-well Vp Contact Cut

13. Jhon P. U Alternate Layout of NOT Gate Gnd Vp X Vp Gnd X X X

14. Jhon P. U NAND2 Layout Gnd Vp X Vp Gnd X X X X

15. Jhon P. U NOR2 Layout Gnd Vp X Vp Gnd X X X X

16. Jhon P. U NAND2-NOR2 Comparison X Vp Gnd X X X X X X X X X Vp Gnd MOS Layout Wiring

17. 2: MIPS Processor Example Slide 20 Activity 2 Sketch a stick diagram for a 4-input NOR gate

18. Jhon P. U Stick Diagram - Example II Power Ground B C Out A