surya_ppt.pptx Inputs and outputs of STA for timing information and design information

Inputs and outputs of STA

1. INPUTS & OUTPUTS OF STA K. SIVA SURYAm BATCH – PD_04

2. What is STA ? Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations without stimulus. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.

3. What are the Inputs and outputs of STA ?

4. NETLIST: it is the gate level netlist or routed netlist. SDC: it consist of timing constraints,optimization constraints ,design constraints and clock exceptions. SPEF : it consist information of net delay. SDF: it consist timing information of all the cells of the design. Libraries: The libraries are having physical information, functionality information and timing information of a each standard cell in a design. Inputs:

5. Outputs: OUTPUT REPORTS : we can see all the reports after running our design. ex: report_global_timing, report_constraints ECO: STA tool performs only timing analysis, it cannot change any logic in our design. We can generate ECO file which contains what are the changes required for fixing all the violations.