Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System

Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.

1. By/ Mostafa Khamis [email protected] Synopsys Fusion Compiler Comprehensive RTL-to-GDSII Implementation System

2. Introduction Fusion Compiler Flow Outline Mostafa Khamis Synopsys Fusion Compiler

3. Introduction

4. There has been a significant uptick in demand for silicon in recent years, driven by market sectors including automotive, artificial intelligence, cloud computing, and internet of things (IoT) that have their own unique mix of design and implementation requirements. Design Challenges: The advancements in process technology towards smaller geometries and design requirements for best performance, lowest power and smaller area in the fastest time, has resulted in a number of design implementation challenges. Emerging Market Segments Mostafa Khamis Synopsys Fusion Compiler

5. The requirements of FinFET and multi-patterning rules must be considered and addressed throughout the design flow. DRC and DFM complexity and growing number of design rules, timing violation, power slacks, and other rules must be applied as early as synthesis in the design cycle. Driving higher utilization and reducing area are key considerations when moving to smaller nodes to justify the cost of migration Achieving high performance is extremely challenging due to aggressive targets, complex clocking mechanisms, and conflicting requirements with power and area. Transistor scaling has resulted in faster transistors and wire delay has become the dominant factor at advanced nodes with highly resistive wires. Optimizing total power has become even more critical due to long battery life requirements of SoC devices and high cooling cost for compute farms. Design Complexity Mostafa Khamis Synopsys Fusion Compiler Regarding, these design challenges, the constant pressure to meet the tight market window is a continuing struggle for designers. The quest for faster full-flow runtimes and convergence, tighter correlation to signoff, and minimal ECO iterations is a key concern for design teams.

6. Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X. Fusion Compiler is built on a compact, single data model that enables seamless sharing of technology and engines for a comprehensive design closure. Fusion Compiler has been built using best-in-class next-generation RTL synthesis, place-and-route and industry-standard golden signoff technologies for designing state-of-the-art system-on-chips (SoCs). Fusion Compiler provides a complete RTL-to-GDSII design system including RTL physical synthesis, design planning, placement, clock tree synthesis (CTS), advanced routing, physical synthesis-based optimization, chip finishing, signoff quality analysis and ECO optimization. Intro to Fusion Compiler Mostafa Khamis Synopsys Fusion Compiler

7. Fusion architecture Synthesis, P&R, signoff Fusion of algorithms, engines, and data model 3 Fusion types: ECO, signoff and test Innovative Products Industry unique Fusion compiler Design compiler NXT New TestMax, and IC validator NXT Market leadership AI-enhanced tools, AI-driven apps Accelerating AI, Automative, 3DIC chips Cloud-ready Synopsys Fusion Design Platform Mostafa Khamis Synopsys Fusion Compiler 20% Better quality-of-results and 2X faster time-to-results

8. 20% better QoR and 2X faster TTR Unified Physical Synthesis (UPS) optimizations that unify best-in-class technologies from next-generation synthesis and place-and-route for best QoR Advanced placement algorithm provides improved design rule check (DRC) count, better pin access, and faster design closure Accurate congestion estimation and prediction using route-driven estimation technology throughout flow for tight correlation and overall convergence Total power optimization throughout the flow including unique technologies such as power-driven re-synthesis, re-constructive leakage and knee-based optimization Accurate signoff quality timing, parasitic extraction, and power analysis engines to eliminate design iterations Advanced physically-aware synthesis optimization with congestion, layer assignment, advanced CTS, and route-based optimization to deliver highest frequencies. Advanced area recovery algorithms from synthesis to post-route optimization Key Highlights of Fusion Compiler Mostafa Khamis Synopsys Fusion Compiler

9. Is built on a single data model and contains both logical and physical information to enable sharing of library, data, constraints, and design intent throughout the implementation flow. Gives synthesis and implementation tools access to each others’ technology including sharing of optimization engines between the two domains. Integrates all synthesis, place-and-route, signoff engines on the single data model which eliminates data transfer and delivers fastest design closure. Enables cross probing different views in the GUI for an enhanced user experience and faster debugging Fusion Data Model Mostafa Khamis Synopsys Fusion Compiler

10. UPS is the nerve center and fundamental backbone for all optimization capabilities within Fusion Compiler, combining the best technologies from next-generation synthesis and place-and-route engines. Fusion Compiler offers unique and innovative solutions that spans both RTL physical synthesis and place-and-route domains including interleaved floorplanning, synthesis, incremental compile, physically-aware data path representation, logic re-synthesis during physical implementation and a common UPS optimization engine that delivers unprecedented QoR and design convergence. These provided technologies such as: next-generation placer - advanced 2D legalizer - concurrent clock and data (CCD) optimization - multi-bit banking and de-banking - total power-centric optimization - automatic non-default rule (NDR). Unified Physical Synthesis (UPS) Mostafa Khamis Synopsys Fusion Compiler

11. CCD Optimization Mostafa Khamis Synopsys Fusion Compiler

12. Fusion Compiler offers a comprehensive RTL-to-GDSII low power-driven flow to optimize both leakage and dynamic power. The infrastructure includes different power optimization technologies throughout the flow. Total Power Optimization Mostafa Khamis Synopsys Fusion Compiler

13. Fusion Compiler enables the fastest turnaround time from RTL-to-GDSII by blurring the boundary between synthesis and physical implementation with a unified physical synthesis optimization flow. Parallelization technologies, multi-threading and distributed processing of key engines throughout the flow utilize hardware resources effectively for fast design convergence and rapid design closure. Incremental compile and placement allow for faster turnaround when netlist or constraint changes are observed. Fastest Time to Results Mostafa Khamis Synopsys Fusion Compiler

14. Fusion Compiler Flow

15. Fusion Compiler Flow Mostafa Khamis Synopsys Fusion Compiler

16. Definition : Design for Test is the art of adding functionality to the chip to enhance its observability and controllability so that it can be effectively tested for correct operation. Observability : ease of observing a node by watching external output pins of the chip Controllability : ease of forcing a node to 0 or 1 by driving input pins of the chip Test Pattern Generation Manufacturing test ideally would check every node in the circuit to prove it is not stuck at 1 or 0. Apply the minimum set of test vectors necessary to prove each node is not stuck Minimum set of test vectors determined through fault simulation using special EDA tools. Automatic Test Pattern Generation: Automatic Test Pattern Generation (ATPG) tools produce a good set of vectors for each block of combinational logic Complete coverage requires a large number of vectors, raising the cost of test Fault Coverage = # of detected faults / # of detectable faults. Most products settle for covering 90+% of potential SA faults Design for Test Mostafa Khamis Synopsys Fusion Compiler

17. Inputs: A hierarchical netlist describing Circuit blocks The logic cells within the blocks, All connections. Goals: Arrange the blocks on a chip (Area Estimation). Decide routing areas (Channel Assignment) Decide the location of the I/O pads w.r.t. block pins, Decide the location and number of the power pads, Decide the type of power distribution, and Decide the location and type of clock distribution. Chip aspect ratio and size to fit in the package cavity and metal levels. Objectives: Minimize the chip area Minimize routing congestion Minimize delay. Floorplanning Mostafa Khamis Synopsys Fusion Compiler

18. Arrange all logic cells within the flexible blocks Objectives: Minimize the total estimated interconnect length Meet the timing requirements for critical nets Minimize the interconnect congestion Additional Objectives: Minimize power dissipation Minimize cross talk between signals There are many placement algorithms: Min-Cut, Simulated Annealing, ….. Placement Mostafa Khamis Synopsys Fusion Compiler

19. Special tools insert multiple buffers with optimal sizing to distribute driver requirements to different elements. In practice, use sufficient design margin on skew and jitter. There are many distribution types techniques to solve the timing variations and the clock timing gap inside the design. Clock Tree Synthesis (CTS) Mostafa Khamis Synopsys Fusion Compiler

20. Physical timing optimization today is all based on ideal clocks timing Timing opt is based on wrong information (like wire load models in the past) Cannot see the real timing situation Even if CTS skew=0, Propagated timing ≠ Ideal timing Clock balancing imposes severe restrictions on timing optimization – for no benefit CTS Problems Mostafa Khamis Synopsys Fusion Compiler

21. Clock Concurrent Technology Mostafa Khamis Synopsys Fusion Compiler

22. Routing Mostafa Khamis Synopsys Fusion Compiler

23. Design Rule Check (DRC): Determines whether the layout of a chip satisfies a series of recommended parameters called design rules. Design rules are physical checks of metal width, pitch and spacing requirement for the different layers with respect to different manufacturing process. LVS: Ensure the functionality of layout by comparing it with the corresponding schematic one generated from netlist. We need the netlist file, GDS (layout database), and LVS rule deck which is a set of code written in Standard Verification Rule Format (SVRF), or TCL verification format (TVF). Design For Manufacturing (DFM): Files (GDS and Rule deck File) It checks extra DRC: Redundant Via insertion, Wire spreading, Wire slotting, and Metal filling. Antenna Rules: They are indicating maximum area of metal to connect to a gate, avoiding antenna effect. IC Validator - Signoff Mostafa Khamis Synopsys Fusion Compiler

24. The assumption of constant VDD and VSS is not valid on chip. Excessive resistance on power supply lines causes ohmic drops which reduces the required voltage for large chips. Intrinsic wire resistance leads to different voltage drops across the VSS distribution network IR drop causes voltage drop which in-turn causes the delaying of the cells causing setup and hold violations. IR Drop – RedHawk - Signoff Mostafa Khamis Synopsys Fusion Compiler

25. Solutions: Reduce the resistance of power lines by using wide metal lines. Use power rings and power straps to distribute the power. Use multiple power pads in parallel to supply the network. And others. IR Drop – RedHawk - Signoff Mostafa Khamis Synopsys Fusion Compiler

26. Files (Reference netlist, Implemented Netlist, .V and .Lib) Comparing implemented netlist with reference netlist (Synthesis stage netlist / golden netlist). We check whether the logic output value given in both stages are same. There are two types: Formal Equivalence Checking: It is a method to find the functional equivalence of one design by comparing with the golden design. These are the areas where equivalence checking is commonly used. It is always carried out using two inputs and result comes out by comparing the functionality of these two input designs. Formal Property Checking It is a method to prove the correctness of design It is carried out by using either using property languages (PSL, SVA) Formality Check - Signoff Mostafa Khamis Synopsys Fusion Compiler

27. Files (SAIF, .V, Lib, UPF and SDF) In Power analysis we calculate the power dissipation. Two types of power dissipation, (i) Leakage Power (ii) Dynamic power. Leakage power is basically static power, for the dynamic power the activity factor is required, which is present in the SAIF (switching activity interchange format) file. We also check for hot spot in the design, the hot spot is basically the small region where the higher power dissipation is present. Power Analysis – PrimePower - Signoff Mostafa Khamis Synopsys Fusion Compiler

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