Chapter 1
Model Order Reduction of Integrated Circuits
in Electrical Networks
Michael Hinze, Martin Kunkel, Ulrich Matthes, and Morten Vierling
AbstractWe consider integrated circuits with semiconductors modeled by mod-
ified nodal analysis and drift-diffusion equations. The drift-diffusion equations
are discretized in space using mixed finite element method. This discretization
yields a high-dimensional differential-algebraic equation. Balancing-related model
reduction is used to reduce the dimension of the decoupled linear network equa-
tions, while the semidiscretized semiconductor models are reduced using proper
orthogonal decomposition. We among other things show that this approach delivers
reduced-order models which depend on the location of the semiconductor in the
network. Since the computational complexity of the reduced-order models through
the nonlinearity of the drift-diffusion equations still depend on the number of
variables of the full model, we apply the discrete empirical interpolation method
to further reduce the computational complexity. We provide numerical comparisons
which demonstrate the performance of the presented model reduction approach. We
compare reduced and fine models and give numerical results for a basic network
with one diode. Furthermore we discuss residual based sampling to construct POD
models which are valid over certain parameter ranges.
1.1 Introduction
Computer simulations play a significant role in design and production of very large
integrated circuits or chips that have nowadays hundreds of millions of semicon-
ductor devices placed on several layers and interconnected by wires. Decreasing
M. Hinze () • U. Matthes • M. Vierling
Department of Mathematics, University of Hamburg, Bundesstraße 55, 20146 Hamburg, Germany
e-mail:
[email protected];
[email protected];
[email protected]
M. Kunkel
Fakultät für Luft- und Raumfahrttechnik, Universität der Bundeswehr München,
Werner-Heisenberg-Weg 39, 85577 Neubiberg, Germany
e-mail:
[email protected]
© Springer International Publishing AG 2017
P. Benner (ed.),System Reduction for Nanoscale IC Design,
Mathematics in Industry 20, DOI 10.1007/978-3-319-07236-4_1
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