testbenchppt because i want to download another ppt.pptx

FIFO example in sv

1. Test bench: Layered approach increase the reusing capability. Verification team build the entire using transaction level model and run test on it. The entire testbench is reusable across the tests, Test layer only needs to modified in order to generate new test.

2. One other problem that often plagues a testbench environment is a race condition between the design and the testbench. Consider the folllwing example. Suppose a testbench is required to wait for a specific response from its DUT. Once it receives the response,  at the same simulation time  it needs to send a set of stimulii back to the DUT. Since Verilog can execute events in various procedural blocks out-of-order, there is a chance that the testbench may send out the stimulii even before the response from the DUT arrives. Program block is a recognition of these differences in goals of writing a design and a test bench. It is meant to facilitate writing of a test bench. A program block is defined within the  program  and  endprogram  keyword pair. It serves three purposes. It provides  an entry point  to the execution of test benches. This is somewhat similar to what a module does for design related constructs. It acts as  a scope  for data defined within this program block. Once again similar to a module, a program block can act as a scope for encapsulating program wide data. Perhaps the most important aspect of a program block is that it is  a syntactic context  that schedules events in the 'Reactive region'. We will see in few minutes what this means and how this can be used to avoid race condition.